HF Divider Topology for Digital PLL Loop Bandwidth and Duty Cycle
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Solution Overview
Problem
Current frequency dividers in wireless communication systems, such as those used in FM receivers, face limitations including asymmetrical duty cycles and insufficient loop bandwidth, which can lead to increased phase noise and instability, particularly in high-frequency applications.
Innovation Solution
A phase locked loop (PLL) system with a frequency divider circuit that includes a divide-by-M circuit with multiple ⅔ cells and a fixed divide-by-2 cell, which maintains a 50% duty cycle and increases loop bandwidth by adjusting the M divider ratio and using dual edge phase-frequency detection, along with a phase correction circuit to address phase errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a frequency divider circuit is used in high-frequency applications, then frequency division is achieved, but asymmetrical duty cycle and insufficient loop bandwidth occur leading to increased phase noise
Solution Approach 1:
The frequency divider is segmented into multiple ⅔ cells connected in series, where each cell contributes to the overall division ratio. This segmentation allows for better control of the duty cycle at each stage, preventing the accumulation of asymmetry that would occur in a single-stage divider.
Solution Approach 2:
Instead of accepting the asymmetrical duty cycle as an inevitable byproduct of frequency division, the patent inverts the approach by designing the divider cells to actively correct and maintain 50% duty cycle. The fixed divide-by-2 cell specifically addresses duty cycle restoration, working against the natural tendency toward asymmetry.
2Reliability
If loop bandwidth is increased to reduce phase noise, then phase noise performance improves, but system stability may be compromised
Solution Approach 1:
The patent implements a programmable frequency divider with adjustable division ratios that can be dynamically configured. This allows the loop bandwidth to be optimized for different operating conditions, enabling wider bandwidth when low phase noise is critical while maintaining stability through adaptive control.
Solution Approach 2:
The phase correction circuit uses feedback to detect and correct phase errors in real-time. This feedback mechanism allows the system to maintain stability even with increased loop bandwidth, as the feedback loop continuously adjusts to prevent instability while permitting wider bandwidth operation.
3Measurement precision
If multiple ⅔ cells are used to achieve precise frequency division, then frequency division accuracy improves, but device complexity increases
Solution Approach 1:
Each ⅔ cell is designed to perform multiple functions: frequency division by 2 or 3, duty cycle maintenance, and phase alignment. This multi-functionality reduces the need for separate correction circuits, thereby limiting the increase in overall device complexity despite using multiple cells.
Solution Approach 2:
The patent changes the fundamental operating parameter of the divider cells from fixed division ratios to programmable ratios. This allows precise frequency division to be achieved by reconfiguring existing cells rather than adding complex hardware, maintaining simplicity while improving accuracy.
Data Source
AI summary
A method of operating a phase locked loop (FIG. 5) for a wireless receiver is disclosed. The method includes receiving a reference signal (503) having a first and a second plurality of cycles and receiving a feedback signal (512) having the first and the second plurality of cycles. The feedback signal is compared (504) to the reference signal. A plurality of phase errors is produced for each cycle of (UP, FIG. 10A) the first plurality of cycles in response to the step of comparing.