Complementary HFET Gate Contact Layout for Low-Resistance Integration
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Solution Overview
Problem
The challenge in existing Planar Optoelectronic Technology (POET) is the difficulty in controlling dry and wet etching processes to effectively remove etch stop layers in semiconductor devices, leading to issues with gate resistance and contact formation in heterojunction field effect transistors (HFETs), particularly in complementary NHFET and PHFET transistors.
Innovation Solution
The use of p-type and n-type ion implants at the ends of refractory metal features to contact the gate and back gate regions of HFET devices, minimizing gate resistance and improving the fabrication process control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used, then existing manufacturing capabilities are maintained, but feature size scaling to 10 nanometer class and below is limited
Solution Approach 1:
The fabrication process is divided into multiple pitch quartering steps (pitch halving, pitch quartering) where each step subdivides the pattern further. This segmented approach enables achieving 10nm class features through iterative refinement rather than requiring single-step high-precision processes, thus resolving the contradiction between feature size scaling and process variability.
Solution Approach 2:
The patent implements nested pitch reduction techniques where pitch quartering is nested within pitch halving processes. Multiple mandrel and spacer layers are nested sequentially, with each layer enabling further feature subdivision. This nested structure allows progressive feature size reduction while maintaining process reliability through standardized repeated steps.
2Productivity
If pitch quartering and merged fin pitch quartering are implemented, then transistor density is enhanced, but fabrication process complexity increases
Solution Approach 1:
The patent merges fin pitch quartering with device formation in integrated process flows. Multiple functions (pitch reduction, fin formation, device patterning) are combined into unified process sequences, thereby increasing transistor density while managing fabrication complexity through process integration rather than separate discrete steps.
Solution Approach 2:
Mandrels and spacers are pre-formed in specific patterns before final device fabrication. This preliminary patterning establishes the pitch-reduced geometry early in the process, enabling subsequent device formation steps to proceed with higher density while maintaining process manageability through staged preparation.
3Length of moving object
If feature sizes are reduced to 10 nanometer class and below, then device capacity increases, but conventional fabrication processes become inadequate
Solution Approach 1:
Mandrels and spacers are introduced as intermediary structures to enable feature size reduction. These temporary structures serve as mediators that define the final feature geometry through self-aligned processes, making 10nm class fabrication feasible by avoiding direct lithographic patterning at such small dimensions and instead using the intermediary mandrel-spacer system to define features.
Data Source
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AI summary
Integrated circuitry is fabricated from semiconductor layers formed on a substrate, which include at least one n-type layer, an inverted p-type modulation doped quantum well (mod-doped QW) structure, a non-inverted n-type mod-doped QW structure, and at least one p-type layer including a first P+-type layer formed below a second P-type layer. An etch operation exposes the second p-type layer. P-type ions are implanted into the exposed second p- type layer. A gate electrode of a n-channel HFET device is formed in contact with the p-type ion implanted region. Source and drain electrodes of the n-channel HFET device are formed in contact with n-type ion implanted regions formed in contact with the n-type mod-doped QW structure. P-channel HFET devices, complementary BICFET devices, stacked complementary HFET devices and circuits and/or logic gates based thereon, and a variety of optoelectronic devices and optical devices can also be formed as part of the integrated circuitry.