HFET Barrier Structure With Material Layer to Suppress Interface Traps
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Solution Overview
Problem
The generation of interface traps at the interface between a compound semiconductor and an insulator in hetero field-effect transistors (HFETs) leads to performance degradation under high voltage applications.
Innovation Solution
Incorporating a material layer made of a metal or semiconductor material between the gate electrode and the drain electrode, reducing the density of interface traps and minimizing the impact of high voltage applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an insulation layer is provided on the barrier layer in HFET, then electrical insulation is achieved, but interface traps are generated at the interface between the compound semiconductor and insulator
Solution Approach 1:
A material layer comprising a metal material or semiconductor material is introduced as an intermediary between the insulation layer and the barrier layer. This intermediate layer acts as a mediator that prevents direct contact between the insulator and compound semiconductor, thereby suppressing interface trap generation while maintaining the electrical insulation function of the insulation layer.
Solution Approach 2:
The original direct interface between the insulation layer and barrier layer is segmented by introducing a separate material layer. This segmentation divides the interface into two distinct interfaces: one between the insulation layer and material layer, and another between the material layer and barrier layer, reducing the harmful effects at each interface.
2Power
If high voltage is applied to HFET, then device performance is improved, but interface traps cause performance degradation
Solution Approach 1:
The material layer is provided in advance as a protective cushioning layer between the insulation layer and barrier layer. This pre-established intermediate structure cushions against the harmful effects of interface trap generation that would otherwise occur during high voltage operation, preventing performance degradation before it can happen.
3Object-generated harmful factors
If a material layer is added between the gate electrode and drain electrode, then interface trap density is reduced, but device structure becomes more complex
Solution Approach 1:
The material layer is designed with specific material parameters (metal or semiconductor material) that enable it to suppress interface trap generation. By carefully selecting materials with appropriate electrical and physical properties, the layer achieves its protective function while minimizing the increase in structural complexity.
Data Source
AI summary
A semiconductor unit includes: a barrier layer including a first compound semiconductor; a channel layer including a second compound semiconductor, and bonded to the barrier layer at a first face; an insulation layer provided on a second face, of the barrier layer, that is on an opposite side of the first face, and having an opening section that exposes the barrier layer; a gate electrode provided to bury the opening section; a source electrode and a drain electrode that are provided on the second face of the barrier layer on both sides of the gate electrode with the gate electrode being interposed; and a material layer including a metal material or a semiconductor material, and provided in contact with the second face of the barrier layer between the gate electrode and the drain electrode.