Nitride Semiconductor HFET and SBD Integration for Noise Reduction
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Solution Overview
Problem
High-speed switching in power semiconductor devices, such as nitride semiconductor HFETs, generates switching noise due to parasitic inductance, leading to device loss and malfunction due to surge voltage/current, which is propagated to the gate line.
Innovation Solution
The nitride semiconductor device integrates a heterojunction field effect transistor (HFET) and a Schottky barrier diode (SBD) in series, with a frame electrode surrounding the outer peripheries to reduce parasitic inductance and shield noise, and includes element isolation insulating layers to prevent reverse leak current, facilitating high-speed switching while suppressing noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If HFET is switched at high speed, then productivity is improved, but switching noise due to parasitic inductance is generated
Solution Approach 1:
The patent extracts and removes the parasitic inductance by integrating the HFET and SBD in a common substrate with shared source/drain regions, eliminating the external connection paths that generate switching noise during high-speed operation
Solution Approach 2:
The patent merges the HFET and SBD into a single integrated device structure where the drain region of the HFET is formed as the anode region of the SBD, creating a unified device that reduces parasitic inductance and enables high-speed switching without generating switching noise
2Productivity
If HFET is switched at high speed, then productivity is improved, but reliability deteriorates due to surge voltage/current
Solution Approach 1:
The patent incorporates an SBD in series with the HFET that provides clamping action to suppress surge voltage and current before they can cause device malfunction or destruction, ensuring reliable high-speed switching operation
Solution Approach 2:
The integration of HFET and SBD in a common substrate with shared regions creates a compact structure that minimizes parasitic inductance, preventing the generation of harmful surge voltage and current during high-speed switching while maintaining device reliability
3Productivity
If HFET is switched at high speed, then productivity is improved, but object-affected harmful factors worsen due to noise propagation to gate line
Solution Approach 1:
The patent removes the external connection paths between HFET and SBD by integrating them in a common substrate, eliminating the pathways through which switching noise could propagate to the gate line and cause malfunction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces switching noise and prevents device malfunction, enabling high-speed operation with reduced loss and increased reliability by minimizing parasitic inductance and shielding external noise.
Implementation Method 1
The HFET realizes the low ON-resistance by utilizing, as a channel, high-mobility and highly-concentrated two-dimensional electron gas (2DEG) generated on an AlGaN/GaN hetero-interface by a piezoelectric polarization
Implementation Method 2
a second Schottky barrier diode having a second anode electrode provided on the second nitride semiconductor layer, forming an electric connection with the second nitride semiconductor layer
Data Source
AI summary
According to one embodiment, a semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and formed of a non-doped or n-type nitride semiconductor having a band gap wider than that of the first nitride semiconductor layer, a heterojunction field effect transistor having a source electrode, a drain electrode, and a gate electrode, a Schottky barrier diode having an anode electrode and a cathode electrode, and first and second element isolation insulating layers. The first element isolation insulating layer has a first end contacting with the drain electrode and the anode electrode, and a second end located in the first nitride semiconductor layer. The second element isolation insulating layer has a third end contacting with the cathode electrode, and a fourth end located in the first nitride semiconductor layer.