Ferroelectric HfO2 Gate Dielectric Crystallization at Thin Dimensions

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Solution Overview

Problem

Existing methods for forming high-k metal gates in semiconductor devices face challenges in achieving phase transformation of amorphous HfO2 to crystalline HfO2 at reduced thicknesses, leading to increased parasitic capacitance and reduced ferroelectricity, which affects device performance.

Innovation Solution

A method involving the application of an electric field during the deposition of a Hf-containing layer and subsequent annealing process to promote the transformation of amorphous HfO2 to ferroelectric orthorhombic HfO2, using a sacrificial layer to facilitate selective deposition and control oxygen vacancies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If the thickness of high-k gate dielectric layer is reduced to scale down device geometry, then device integration density is improved, but parasitic capacitance increases and ferroelectricity is reduced

Engineering Contradiction:
Improvegate dielectric layer thicknessVSAvoidferroelectricity
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent applies parameter changes by modifying the deposition conditions (applying electric field during deposition) and thermal treatment (annealing at specific temperatures) to transform the gate dielectric layer from amorphous to crystalline phase, thereby maintaining ferroelectricity even at reduced thicknesses

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent utilizes phase transitions by transforming the HfO2 gate dielectric layer from amorphous phase to crystalline phase through controlled annealing processes, which enables the material to exhibit ferroelectric properties at thinner dimensions

Inventive Principle:
Principle #36Phase transitions

2Ease of manufacture

If conventional deposition methods are used for Hf-containing layer, then manufacturing simplicity is maintained, but phase transformation to ferroelectric orthorhombic HfO2 is insufficient

Engineering Contradiction:
Improvedeposition process simplicityVSAvoidphase transformation control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by depositing the Hf-containing layer under an electric field before the annealing process, which prepares the material structure in advance to facilitate subsequent phase transformation to ferroelectric orthorhombic phase during annealing

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses an intermediary approach by introducing a sacrificial layer that facilitates selective deposition and controls oxygen vacancies during the deposition process, thereby enabling better phase transformation control

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances the ferroelectric properties of high-k gate dielectric layers, reducing subthreshold swing and parasitic capacitance, thereby improving the performance of field-effect transistors.

Implementation Method 1

application of an electric field during the deposition of a Hf-containing layer and subsequent annealing process to promote the transformation of amorphous HfO2 to ferroelectric orthorhombic HfO2

Methodology Applied
Scientific EffectFerroelectric phase transformation: Phase Change

Implementation Method 2

subsequent annealing process to promote the transformation of amorphous HfO2 to ferroelectric orthorhombic HfO2

Methodology Applied
Scientific EffectCrystallization: Crystallisation

Data Source

PatentUS20250311271A1Fabrication of field effect transistors with ferroelectric materials
Publication Date: 2025.10.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250311271A1 patent drawing
  • US20250311271A1 patent drawing
  • US20250311271A1 patent drawing

AI summary

A semiconductor structure includes gate spacers disposed over a semiconductor layer, a hafnium-containing dielectric layer, where a first portion of the hafnium-containing dielectric layer having a first thickness is disposed over the semiconductor layer and a second portion of the hafnium-containing dielectric layer having a second thickness is disposed along sidewalls of the gate spacers, and where the first thickness is greater than the second thickness, and a metal gate electrode disposed over the hafnium-containing dielectric layer and between the gate spacers.