HFPC Decoding Structure for High-Rate Flash Memory ECC
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Solution Overview
Problem
Conventional encoding methods are not well-suited for supporting high code rates in flash memory devices, particularly for both hard decoding and soft decoding, leading to complex and costly implementations, and are ineffective in correcting high raw bit error rates under stress conditions.
Innovation Solution
The implementation of a modified half product code, referred to as a half folded-product code (HFPC), which enables high code rates and efficient error correction by using multiple component codes, such as Bose-Chaudhuri-Hocquenghem (BCH) codes, for both hard and soft decoding, thereby improving read performance and reducing implementation complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional encoding methods (e.g., LDPC codes) are used to achieve high code rates, then code rate is improved, but implementation complexity increases considerably
Solution Approach 1:
The patent segments the encoding process into multiple independent component codes (e.g., several BCH codes) that operate in parallel. Each component code handles a portion of the data, allowing high code rates to be achieved without requiring a single complex encoding structure. This segmentation reduces overall implementation complexity while maintaining high code rate capability.
2Adaptability or versatility
If conventional encoding methods are used for high code rates, then code rate is improved, but cost increases
Solution Approach 1:
The patent employs multiple inexpensive component codes (such as BCH codes) that can be implemented using simple, cost-effective hardware or software. Rather than using a single complex expensive code structure, the system uses multiple simpler codes that are cheaper to implement individually, reducing overall manufacturing and implementation costs while achieving the desired high code rate.
3Reliability
If strong ECC is used to correct high raw bit error rates, then error correction capability is improved, but programming speed decreases
Solution Approach 1:
The patent segments the error correction function across multiple component codes that can operate independently and in parallel. During programming, each component code processes a portion of the data simultaneously, maintaining high programming speed while collectively providing strong error correction capability for high raw bit error rates. This parallel segmented approach avoids the sequential processing bottleneck of single strong ECC schemes.
4Reliability
If strong ECC is used under high stress conditions, then reliability is improved, but digital signal processing complexity increases
Solution Approach 1:
The patent employs component codes (such as BCH codes) that possess inherent error correction properties and can autonomously correct errors without requiring complex external DSP processing. Each component code self-services its portion of the data, providing reliable error correction under high stress conditions while minimizing the need for complex centralized digital signal processing infrastructure.
Data Source
AI summary
Various implementations described herein relate to systems and methods for performing error correction in a flash memory device by determining suggested corrections by decoding a codeword. In addition, whether a first set of the suggested corrections obtained based on a first component code of the plurality of component codes agree with a second set of the suggested corrections obtained based on a second component code of the plurality of component codes is determined. One of accepting the first set of the suggested corrections or rejecting the first set of the suggested corrections is selected based on whether the first set of the suggested corrections and the second set of the suggested corrections agree.