Horizontal Gate All Around Isolation via Buried Oxide Formation
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Solution Overview
Problem
Conventional methods for forming horizontal gate all around (hGAA) and fin field effect transistor (FinFET) device structures face challenges with parasitic capacitance and leakage, as dopant implantation can hinder epitaxial growth and may not adequately reduce parasitic effects, and thermal oxidation processes exceed the thermal budgets of stacked lattice matched channels.
Innovation Solution
A superlattice structure comprising silicon and silicon germanium layers with varying germanium content is formed on a substrate, where the higher germanium content layers are oxidized to create a buried oxide layer, enhancing device isolation and reducing parasitic leakage and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dopant implantation is used to suppress parasitic leakage, then leakage is reduced, but epitaxial growth is hindered and device variability increases
Solution Approach 1:
The patent extracts the dopant implantation step from the process and replaces it with in-situ doped silicon germanium layer deposition. This removes the harmful effect of dopant implantation on epitaxial growth while maintaining the beneficial effect of dopant presence for leakage suppression. The dopants are introduced during the epitaxial growth process itself rather than through subsequent implantation.
Solution Approach 2:
The patent changes the method of dopant introduction from post-growth implantation to in-situ incorporation during epitaxial growth. This parameter change in the doping process allows dopants to be uniformly distributed without disrupting the epitaxial structure, resolving the contradiction between leakage suppression and growth quality.
2Reliability
If thermal oxidation is used to treat parasitic devices, then parasitic effects are reduced, but temperatures exceed the thermal budget of stacked lattice matched channels
Solution Approach 1:
The patent extracts the need for high-temperature thermal oxidation by preventing parasitic device formation in the first place through selective layer removal and buried oxide formation. This eliminates the requirement for subsequent high-temperature treatments that would exceed the thermal budget of the stacked channels.
Solution Approach 2:
The patent performs preliminary actions during the epitaxial growth process itself - forming buried oxide layers and selectively removing sacrificial layers - to prevent parasitic device formation before it occurs. This preliminary prevention avoids the need for later high-temperature thermal oxidation treatments.
3Ease of manufacture
If conventional isolation methods are used, then device isolation is achieved, but parasitic capacitance and leakage are not adequately reduced
Solution Approach 1:
The patent uses composite material structures - specifically alternating layers of silicon and silicon germanium with different germanium contents - to achieve both isolation and parasitic reduction. The buried oxide layers formed from high-germanium silicon germanium provide electrical isolation, while the graded germanium composition manages stress and reduces parasitic effects throughout the structure.
Solution Approach 2:
The patent applies local quality by varying the germanium content in different silicon germanium layers - lower germanium content (20-40%) in some layers and higher germanium content (50-80%) in others. This local variation in material composition allows different regions to serve different functions: stress management, selective oxidation for buried oxide formation, and parasitic reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a substantially defect-free stacked channel structure, increasing circuit density, reducing parasitic leakage and capacitance, and lowering power consumption while maintaining geometric benefits in current density per square micrometer.
Implementation Method 1
the higher germanium content SiGe layers are oxidized to form buried oxide (BOX) layers
Data Source
AI summary
Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.