hGAA Nanowire Air Gap Spacer Formation for Parasitic Capacitance
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Solution Overview
Problem
The challenge in producing next-generation semiconductor devices lies in reliably forming sub-half micron features with high aspect ratios, particularly in hGAA structures, where managing parasitic capacitance between the metal gate and source/drain regions is crucial to prevent degraded device performance.
Innovation Solution
A method involving the deposition of dielectric material on both sides of a stack with recesses, followed by the removal of excess material, and the formation of a stressor layer with air gaps to control parasitic capacitance, utilizing a plasma processing chamber to create nanowire structures with reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar MOSFET architecture is used, then manufacturing is simpler, but short channel effect increases significantly
Solution Approach 1:
The patent transitions from conventional planar 2D channel structure to a 3D vertical nanowire structure with gate-all-around configuration. The nanowire channel extends vertically from the substrate, and the gate electrode completely surrounds the nanowire channel in three dimensions, providing superior electrostatic control and reducing short channel effects compared to planar devices.
2Reliability
If hGAA structures with metal gate are used, then electrostatic control is improved, but parasitic capacitance between gate and source/drain increases
Solution Approach 1:
The patent applies different dielectric materials with different permittivity values at different locations around the nanowire channel. High-k dielectric material is used in regions where strong electrostatic control is needed, while low-k or air gap dielectric material is used in regions where parasitic capacitance reduction is prioritized, particularly near the source and drain regions.
Solution Approach 2:
The patent varies the permittivity parameter of the gate dielectric material as a function of position around the nanowire. By changing the dielectric constant from high to low in different angular positions, the design optimizes the trade-off between electrostatic control (requiring high permittivity) and parasitic capacitance reduction (requiring low permittivity).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and minimizes device leakage, enhancing the performance and reliability of horizontal gate-all-around (hGAA) semiconductor devices by forming nanowire structures with controlled parasitic capacitance.
Implementation Method 1
utilizing a plasma processing chamber to create nanowire structures with reduced parasitic capacitance
Data Source
AI summary
Embodiments provide methods for forming nanowire structures, such as, for example, horizontal gate-all-around (hGAA) structures. In one embodiment, a method includes selectively etching material from a stack disposed on a material layer located on a substrate with a plasma to create recesses on each of first and second sides of the stack and depositing a dielectric material on the first and second sides. The stack includes repeating pairs of first and second layers. The method also includes removing the dielectric material from the first and second sides, where the dielectric material remains in the recesses of the first and second sides, and selectively depositing a stressor layer on regions of the first and second sides which are unprotected by the dielectric material to form gaps between the stressor layer and the dielectric material remaining in the recesses of the first and second sides.