Hardware-Guided Scheduling for Temperature-Constrained Processor Cores
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Solution Overview
Problem
Existing scheduling techniques for hybrid processor architectures are inefficient as they rely solely on core temperatures to determine performance, leading to incorrect and inefficient decisions.
Innovation Solution
The implementation of a hardware-guided scheduling (HGS) interface that communicates dynamic processor capabilities to the operating system based on power and thermal constraints, allowing for closed-loop control of resource allocation and operating point selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If core temperature is used as the sole criterion for scheduling decisions, then implementation simplicity is maintained, but scheduling efficiency and accuracy deteriorate
Solution Approach 1:
The patent extends the scheduling decision parameters from only core temperature to include multiple dimensions: core type (homogenous vs. hybrid), temperature characteristics, power consumption, and performance capabilities. This multi-parameter approach transforms the scheduling system from a simple temperature-based decision to a comprehensive performance-aware scheduling mechanism, resolving the contradiction by accepting increased complexity to achieve significant improvements in scheduling accuracy and efficiency.
2Loss of information
If only temperature information is considered for core selection, then information processing overhead is reduced, but decision accuracy deteriorates
Solution Approach 1:
The patent implements preliminary characterization of core performance capabilities and temperature characteristics during system initialization or idle periods. This pre-computed information is stored and used during scheduling decisions, allowing the system to make accurate predictions without real-time information processing overhead. The preliminary action resolves the contradiction by preparing performance data in advance, so that scheduling decisions can be made quickly with high accuracy.
3Measurement precision
If dynamic feedback of per-core characteristics is implemented, then scheduling accuracy is improved, but system complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the scheduler continuously monitors core performance, temperature, and power consumption, then uses this feedback to dynamically adjust scheduling decisions. The feedback loop includes performance measurement, comparison against targets, and adaptive adjustment of scheduling policies. This resolves the contradiction by establishing a closed-loop control system that improves accuracy through continuous learning while managing complexity through systematic feedback processing.
Data Source
AI summary
An apparatus and method for temperature-constrained frequency control and scheduling. For example, one embodiment of a processor comprises: a plurality of cores; power management circuitry to control a frequency of each core of the plurality of cores based, at least in part, on a temperature associated with one or more cores of the plurality of cores, the power management circuitry comprising: a temperature limit-driven frequency controller to determine a first frequency limit value based on a temperature of a corresponding core reaching a first threshold; frequency prediction hardware logic to predict a temperature-constrained frequency of the corresponding core based on the first frequency limit value and an initial frequency limit value; and performance determination hardware logic to determine a new performance value for the corresponding core based on the temperature-constrained frequency, the new performance value to be provided to a task scheduler.