Hemispherical Grained Silicon Capacitor Grain Control
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Solution Overview
Problem
Conventional capacitor designs for semiconductor devices, such as trench and stack capacitors, face challenges in miniaturization while maintaining voltage storage requirements, leading to inefficiencies and low yields due to complex manufacturing processes and potential grain merging issues in hemispherical grained silicon growth.
Innovation Solution
A method involving a substrate with a container structure having varying dopant concentrations and grain dimensions is employed, where phosphorous is implanted to enhance hemispherical grained silicon growth, preventing bridging and merging by controlling grain size, and using conventional processes to form a capacitor structure with improved capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional capacitor designs are miniaturized to increase circuit density, then device complexity and manufacturing difficulty increase, but voltage storage requirements cannot be maintained
Solution Approach 1:
The capacitor structure is divided into multiple cylindrical containers arranged in a stack, with each container holding separate hemispherical grained silicon grains. This segmentation allows independent formation and control of each grain, simplifying the manufacturing process while maintaining high density through vertical stacking
Solution Approach 2:
The invention transitions from planar capacitor layouts to vertical stack configurations, utilizing the third dimension (height) to increase circuit density. Multiple capacitor units are stacked vertically within a single footprint area, effectively multiplying the capacitance per unit area without increasing manufacturing complexity
2Reliability
If hemispherical grained silicon is grown in conventional capacitor structures, then grain merging and shorting occur, but device yields remain low
Solution Approach 1:
The container structures are designed with locally optimized geometries including varying wall thicknesses and internal configurations tailored to control silicon grain growth patterns. The cylindrical containers provide localized constraints that prevent grain merging at critical interfaces while allowing proper grain formation in other regions
Solution Approach 2:
The container walls act as intermediary structures between adjacent hemispherical grained silicon grains, physically separating them and preventing electrical shorting. These containers serve as dielectric barriers that maintain electrical isolation while allowing the grains to achieve their required size for adequate capacitance
3Productivity
If capacitor size is reduced to increase devices per wafer, then fabrication throughput increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
The container structures are formed in advance using established lithography and etching processes with well-defined geometries. These pre-formed containers serve as templates that guide subsequent silicon deposition and grain growth, ensuring precise dimensional control without requiring ultra-precise process steps at each stage
Solution Approach 2:
The invention utilizes controlled changes in deposition parameters and thermal processing conditions during hemispherical grained silicon formation. By adjusting temperature profiles, deposition rates, and annealing conditions, the grain size and morphology are precisely controlled within the constrained container geometries, achieving the required manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases device yields and maintains compatibility with existing technology, preventing grain merging and shorting, thus enhancing the manufacturing efficiency and output of semiconductor devices.
Implementation Method 1
phosphorous is implanted to enhance hemispherical grained silicon growth
Implementation Method 2
formation of hemispherical grained silicon material having a first grain dimension near the vicinity of the lower surface and formation of hemispherical grained silicon material having a second grain dimension near a vicinity of the upper surface
Data Source
AI summary
A dynamic random access memory device including a capacitor structure, e.g., trench, stack. The device includes a substrate (e.g., silicon, silicon on insulator, epitaxial silicon) having a surface region. The device includes an interlayer dielectric region overlying the surface region. In a preferred embodiment, the interlayer dielectric region has an upper surface and a lower surface. The device has a container structure within a portion of the interlayer dielectric region. The container structure extends from the upper surface to the lower surface. The container structure has a first width at the upper surface and a second width at the lower surface. The container structure has an inner region extending from the upper surface to the lower surface. In a specific embodiment, the container structure has a higher dopant concentration within a portion of the inner region within a vicinity of the lower surface and on a portion of the inner region near the vicinity of the lower surface. The device also has a doped polysilicon layer overlying the inner region of the trench structure. The device has a first hemispherical grained silicon material having a first grain dimension near the vicinity of the lower surface and a second hemispherical grained silicon material having a second grain dimension near a vicinity of the upper surface of the container structure. In a preferred embodiment, the first grain dimension has an average size of no greater than about ½ of an average size of the second grain dimension to prevent any bridging of any portions of the hemispherical grained silicon material within the vicinity of the lower surface.