High Hole Mobility Transistor Band Adjustment Layer
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Solution Overview
Problem
Existing high hole mobility transistors face challenges in achieving uniformity and low channel resistance due to difficulties in controlling gate recess depth and uniformity, leading to degraded electrical parameters.
Innovation Solution
A high hole mobility transistor design that includes a band adjustment layer on the channel region, which is N-type doped to lower the energy band, eliminating the two-dimensional hole gas and forming an enhancement mode transistor, thereby improving uniformity and reducing channel resistance without relying on the conventional gate recess process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If gate recess process is used to form enhancement mode HHMT, then the transistor can be turned off and standby power dissipation is reduced, but the manufacturing precision deteriorates due to difficulty in controlling gate recess depth and uniformity
Solution Approach 1:
The patent changes the doping parameter (adding N-type doping) to the gate structure to achieve enhancement mode operation without requiring gate recess. The N-type doping in the gate region modifies the electrical characteristics, allowing the transistor to be turned off while avoiding the manufacturing precision issues of gate recess processing.
Solution Approach 2:
The patent extracts the gate recess process from the fabrication sequence and replaces it with N-type doping. This removes the problematic step that causes non-uniformity while preserving the desired enhancement mode functionality.
2Ease of operation
If gate recess process is used to form enhancement mode HHMT, then the transistor can be turned off, but the device complexity increases due to additional processing steps and parameter control requirements
Solution Approach 1:
The patent removes the complex gate recess processing steps and replaces them with a simpler N-type doping process. This extraction of the problematic process simplifies the overall fabrication sequence while maintaining the transistor's switching capability.
Solution Approach 2:
The patent replaces the mechanical/physical gate recess process with a chemical doping process. This substitution eliminates the need for precise mechanical etching and depth control, reducing fabrication complexity.
3Ease of operation
If gate recessed region is created, then enhancement mode operation is achieved, but channel resistance increases
Solution Approach 1:
The patent changes the doping parameter in the gate region (adding N-type doping) to achieve enhancement mode operation without creating a gate recessed region. This parameter change maintains good channel conductivity while enabling the desired switching mode.
Solution Approach 2:
The patent applies N-type doping locally in the gate region to achieve enhancement mode operation without affecting the overall channel structure. This localized modification improves switching capability while maintaining low channel resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances the uniformity and maintains low channel resistance, making the high hole mobility transistor safer with lower standby power dissipation, reduced circuit complexity, and lower production costs compared to conventional devices.
Implementation Method 1
Due to the band bending at the heterojunction, a potential well is formed at the bending conduction band so that a two-dimensional electron gas (2DEG) is formed in the potential well
Implementation Method 2
The band adjustment layer is an N-type doped III-V semiconductor... which is N-type doped to lower the energy band, eliminating the two-dimensional hole gas
Data Source
AI summary
A high hole mobility transistor includes a substrate, a back-barrier layer, a conducting layer, a doping layer, a gate electrode, source/drain electrodes, and a band adjustment layer. The back-barrier layer is disposed on the substrate. The conducting layer is disposed on the back-barrier layer. A channel region is disposed in the conducting layer and is adjacent to the interface between the conducting layer and the back-barrier layer. The doping layer is disposed on the conducting layer. The gate electrode is disposed on the doping layer. The source/drain electrodes are disposed on opposite sides of the gate electrode. The band adjustment layer is disposed on the doping layer and electrically connected to the gate electrode. The band adjustment layer is an N-type doped III-V semiconductor.