Hibernation Circuit with Sub-Processor for Low-Power Data Evacuation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing information processing systems consume excessive power during hibernation due to processor involvement in data evacuation processes.
Innovation Solution
Implementing a sub-processing circuit to execute data evacuation from DRAM to SRAM, utilizing a hibernation circuit that consumes less power and operates at a slower speed, while the main processing circuit maintains power to SRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the main processing circuit executes evacuation processing, then the processing speed is high, but the electric power consumption is excessive
Solution Approach 1:
The processing circuit is segmented into a main processing circuit for general-purpose high-speed processing and a sub-processing circuit for specialized evacuation processing. The sub-processing circuit handles the specific task of evacuating data from DRAM to SRAM, allowing the main processing circuit to remain in a low-power state during hibernation while evacuation processing occurs.
Solution Approach 2:
A sub-processing circuit acts as an intermediary between the main processing circuit and the memory system. This intermediary handles the evacuation processing task, enabling the main processing circuit to consume minimal power during hibernation while still achieving data evacuation functionality.
2Use of energy by moving object
If a dedicated sub-processing circuit is used for evacuation processing, then the electric power consumption is reduced, but the processing speed becomes slower
Solution Approach 1:
The processing system is divided into two specialized circuits: a main processing circuit optimized for high-speed general-purpose processing, and a sub-processing circuit optimized for low-power evacuation processing. Each circuit performs its designated function with appropriate performance characteristics for its specific task.
Solution Approach 2:
Different parts of the processing system have different quality characteristics tailored to their specific functions. The sub-processing circuit has low-power characteristics optimized for evacuation tasks, while the main processing circuit maintains high-speed characteristics for general processing, allowing each component to operate at its optimal performance point.
3Speed
If all data is stored in volatile memory, then the access speed is fast, but the power consumption during idle state is high
Solution Approach 1:
Before the system enters hibernation mode, the sub-processing circuit performs preliminary evacuation of necessary data from volatile DRAM to SRAM. This preliminary action ensures that critical data is preserved in a low-power state, allowing the main processing circuit to cut power to DRAM while maintaining fast access to essential data in SRAM during hibernation.
Solution Approach 2:
The system changes the storage parameter for different types of data based on power state requirements. Frequently accessed or critical data is stored in SRAM for low-power retention, while other data resides in DRAM for high-speed access during active operation. This dynamic parameter change optimizes both speed and power consumption based on operational state.
Data Source
AI summary
The information processing device includes a CPU, DRAM, SRAM and hibernation circuitry. The hibernation circuit executes an evacuation processing of reading out particular data which is data stored in DRAM and storing the particular data in SRAM when a predetermined execution condition for hibernation is satisfied. CPU shuts off the electric power supply to DRAM while maintaining the electric power supply to SRAM after the evacuation processing is completed. When startup, CPU reads out the particular data stored in SRAM when the particular data is stored in SRAM.