Hidden Per-Bank Refresh Control for Memory Bandwidth and Power
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Solution Overview
Problem
Existing memory devices face inefficiencies in refresh operations, leading to increased power consumption and reduced bandwidth due to bulk refresh commands that do not account for the finer granularity needed in managing individual banks.
Innovation Solution
Implementing on-die refresh control circuitry to manage per-bank refresh operations in a hidden mode, supplementing host controller operations with finer granularity, allowing for independent and concurrent refresh commands on idle banks, thereby reducing power consumption and enhancing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bulk refresh commands are used to refresh multiple banks simultaneously, then refresh operation speed is improved, but power consumption increases and bandwidth is reduced
Solution Approach 1:
The memory device divides the refresh operation into bank-level segments, allowing individual banks to be refreshed independently rather than forcing a choice between bulk refresh (fast but high power) or individual refresh (low power but slow). Each bank can be refreshed at optimal intervals based on its specific needs, achieving both power efficiency and adequate refresh speed.
Solution Approach 2:
The system dynamically adjusts refresh timing and granularity based on bank activity status. Idle banks receive refresh operations during periods when other banks are active, optimizing the balance between refresh completion speed and power consumption by adapting to real-time operational conditions.
2Speed
If bulk refresh commands are used to refresh multiple banks simultaneously, then refresh operation speed is improved, but available bandwidth for data operations is reduced
Solution Approach 1:
By segmenting refresh operations to the bank level, the system can interleave refresh commands with data operations across different banks. This allows data transactions to proceed on active banks while refresh operations occur on idle banks, maintaining high bandwidth utilization without sacrificing refresh effectiveness.
Solution Approach 2:
The system maintains continuous useful action by ensuring that while some banks are undergoing refresh, other banks remain available for data operations. This continuous interleaving of refresh and data operations across multiple banks ensures both refresh requirements are met and bandwidth is maximized.
3Use of energy by moving object
If individual bank refresh operations are performed independently, then power consumption is reduced and bandwidth is enhanced, but refresh coordination complexity increases
Solution Approach 1:
Each bank is equipped with its own refresh control logic that can autonomously determine when refresh operations are needed based on its activity status. This self-service approach eliminates the need for complex centralized coordination, as each bank manages its own refresh timing independently based on simple activity detection.
Solution Approach 2:
The system uses feedback from bank activity status to automatically adjust refresh timing. When a bank becomes idle, it triggers a refresh operation; when a bank is active, refresh is deferred. This feedback mechanism simplifies coordination by using real-time operational information to automatically optimize refresh scheduling without complex control logic.
Data Source
AI summary
An integrated circuit (IC) memory device includes an array of storage cells configured into multiple banks. Interface circuitry receives refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode. On-die refresh control circuitry selectively generates local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode. Mode register circuitry stores a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode. The interface circuitry includes backchannel control circuitry to transmit a corrective action control signal during operation in the second refresh mode.