Hidden Memory Management via 3D Stacked DRAM and Page Tables
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Solution Overview
Problem
Embedded DRAM (eDRAM) integrated with processors has a higher cost-per-bit compared to standalone DRAM chips, and existing high bandwidth memory (HBM) technologies do not efficiently address the need for high capacity hidden memory accessible only by the processor for secure and virtualized computing environments.
Innovation Solution
The implementation of hidden memory using 3D stacked DRAM with hidden page tables, where the memory is accessible only by the processor and not by user applications, providing a large capacity for secure storage and virtualization, including error correction and integrity management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If eDRAM is integrated with the processor on the same die, then access performance and bandwidth are improved, but cost-per-bit increases
Solution Approach 1:
The memory system is segmented into different types of memory with distinct functions: HBM memory for high-performance access and eDRAM for cost-effective storage. This allows the system to optimize between performance and cost by using each memory type where it provides the most value.
Solution Approach 2:
The patent introduces a new dimension to memory hierarchy by integrating hidden memory pages within the processor die that are inaccessible to user applications. This creates a private memory space for virtualization and security functions, adding a new layer to the traditional memory hierarchy.
2Power
If HBM technology is used for high bandwidth memory, then bandwidth and power efficiency are improved, but capacity for hidden memory is insufficient
Solution Approach 1:
The patent merges HBM technology with eDRAM and introduces hidden memory pages within the processor die. This combination allows the system to achieve high bandwidth and low power consumption from HBM while adding the capacity and security features of hidden memory through eDRAM and integrated memory pages.
Solution Approach 2:
The memory system is designed to serve multiple functions simultaneously: HBM provides high bandwidth for general computing, eDRAM provides cost-effective capacity, and hidden memory pages provide secure storage for virtualization. This multi-functionality allows a single memory system to address diverse requirements.
3Reliability
If hidden memory is made accessible only by the processor, then security and virtualization capabilities are improved, but memory management complexity increases
Solution Approach 1:
The patent introduces hidden page tables as an intermediary structure between the processor and hidden memory pages. These page tables manage the mapping and access to hidden memory, providing a systematic way to handle the complexity of restricted memory access while maintaining security.
Solution Approach 2:
The patent creates copies of memory management structures (page tables) specifically for hidden memory, separate from the main memory management system. This allows independent management of hidden memory security and access control without complicating the overall memory management architecture.
Data Source
Figure 1A~2A
Figure 2B
Figure 3~4
AI summary
An embodiment of an apparatus may include a processor, memory communicatively coupled to the processor, and circuitry communicatively coupled to the processor and the memory, the circuitry to manage a portion of the memory as hidden memory outside a range of physical memory accessible by user applications, and control access to the hidden memory from the processor with hidden page tables. Other embodiments are disclosed and claimed.