Hidden Refresh of Weak Memory Cells in DRAM
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Solution Overview
Problem
In solid state memory systems, particularly DRAM devices, shrinking cell sizes lead to increased variability in access transistor leakage and reduced storage capacitance, resulting in shorter data retention times and longer write-recovery times, which can decrease system performance and require techniques to hide or manage these issues.
Innovation Solution
Implementing a method and system that uses a memory interface device with a counter to measure and manage write-recovery times for weak memory cells, allowing for longer write-recovery times by concurrently executing activation-precharge cycles and employing an address match table to replace faulty cells with spare cells, thereby maintaining system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cell sizes are shrunk to increase memory capacity, then storage density is improved, but data retention time deteriorates due to increased transistor leakage and reduced storage capacitance
Solution Approach 1:
The patent applies preliminary action by measuring write-recovery times during manufacturing and proactively identifying weak cells before they cause errors. Weak cells are detected and marked during fabrication testing, allowing the system to prepare compensation mechanisms in advance without affecting normal operation.
Solution Approach 2:
The patent introduces an intermediary approach by using a counter to measure write-recovery times and a mapping structure to track weak cell locations. These intermediary components enable the system to manage cell weaknesses without changing the physical cell structure or requiring complex hardware modifications.
2Quantity of substance
If cell sizes are shrunk to increase memory capacity, then storage density is improved, but write-recovery time increases for weak cells due to higher transistor on-resistance
Solution Approach 1:
The patent applies preliminary action by measuring write-recovery times during manufacturing and proactively identifying weak cells before they cause errors. Weak cells are detected and marked during fabrication testing, allowing the system to prepare compensation mechanisms in advance without affecting normal operation.
Solution Approach 2:
The patent changes operational parameters by dynamically adjusting write-recovery time expectations based on measured cell characteristics. Instead of using a fixed timing parameter, the system adapts the write-recovery time parameter individually for each cell based on its measured performance, thereby optimizing both performance and reliability.
3Area of moving object
If access transistor size is reduced to shrink cell size, then storage density is improved, but transistor leakage increases causing shorter data retention time
Solution Approach 1:
The patent applies preliminary action by measuring write-recovery times during manufacturing and proactively identifying weak cells before they cause errors. Weak cells are detected and marked during fabrication testing, allowing the system to prepare compensation mechanisms in advance without affecting normal operation.
Data Source
AI summary
In an example, the present invention provides a computing system. The system has a memory interface device comprising a counter, a dynamic random access memory device coupled to the memory interface device. The device comprises a plurality of banks, each of the banks having a subarray, each subarray having a plurality of memory cells. The device has a data interface coupled to the plurality of banks. The device has an address interface coupled to the plurality of banks, and a particular pre-charge command configured to be transferred to the memory interface device. The counter is adapted to count a measured time duration from a first time when data are available at the data interface to a second time when a pre-charge command is received by the address interface.