Hidden Sawbow Lines in Semiconductor Security
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Solution Overview
Problem
Existing semiconductor devices are vulnerable to hacking techniques that exploit sawbow lines created during the cutting of wafers, allowing unauthorized access to data stored in memory chips.
Innovation Solution
The implementation of sawbow lines hidden by overlapping metal layers, with resistors and logic circuits configured to disable test or memory/factory program modes when the sawbow lines are cut, making it difficult for hackers to locate and access the data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If sawbow lines are made visible and accessible for testing and programming during manufacture, then ease of operation is improved, but security against hacking deteriorates
Solution Approach 1:
The patent applies dimensionality change by moving sawbow lines from the same plane as visible features to different metal layers in the vertical dimension. Sawbow lines are placed on intermediate metal layers between top and bottom metal layers, making them invisible from external views while maintaining electrical connectivity for testing and programming operations.
Solution Approach 2:
The patent uses an intermediary approach by introducing resistors as mediator components connected to sawbow lines. These resistors are configured to disable test mode and factory program mode when the sawbow lines are cut, thereby preventing hackers from utilizing the sawbow lines for unauthorized access while allowing legitimate manufacturing processes to complete before cutting.
2Productivity
If test modes and program modes are enabled for manufacturing operations, then productivity is improved, but security against unauthorized access deteriorates
Solution Approach 1:
The patent implements preliminary anti-action by pre-configuring resistors to disable test mode and factory program mode. Before the wafer is cut and before any hacking can occur, the resistors are already in place to prevent unauthorized access. When sawbow lines are cut during normal manufacturing, the resistors automatically disable the modes, ensuring that even if hackers attempt to use these lines, the protective mechanism is already active.
3Object-affected harmful factors
If multiple metal layers are used to hide sawbow lines, then security is improved, but device complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension created by multiple metal layers to conceal sawbow lines. By placing sawbow lines on intermediate metal layers (such as second or third metal layers) rather than on the topmost visible layer, the structure provides natural hiding without requiring additional complex protective elements. The overlapping arrangement of metal layers creates a hierarchical structure where upper layers mask lower layers from external observation.
Data Source
AI summary
A semiconductor die includes a circuit, a plurality of metal layers, a first sawbow line coupled to the circuit, and a second sawbow line coupled to the circuit. The first sawbow line is hidden under a first metal layer of the plurality of metal layers when the first sawbow line is in a cut state. The second sawbow line is hidden under the first metal layer or a second metal layer of the plurality of metal layers when the second sawbow line is in a cut state. The first sawbow line and the second sawbow line are on different ones of the plurality of metal layers. A number of pull-down or pull-up resistors may be included to set the logical states of the sawbow lines, in order to disable a predetermined mode of operation of the die when a wafer including the die is cut. The sawbow lines may carry a variety of types of signals (e.g., analog, digital, random, ground, supply) that makes the nature and value of them extremely hard to detect/hack.