Hierarchical Accelerator Scheduling for Die Size and Complexity Tradeoffs
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Solution Overview
Problem
Scheduling tasks in a heterogeneous computing environment is challenging due to conflicting considerations of die size and scheduling complexity, leading to under-utilization of accelerator resources.
Innovation Solution
Implementing a hierarchical task scheduler with a coarse scheduling circuit module and fine scheduling circuit modules to partition and schedule tasks efficiently, optimizing for makespan and supporting diverse accelerator technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If tasks are partitioned into fine-grained sub-tasks to reduce die size, then die size is reduced, but scheduling complexity increases exponentially
Solution Approach 1:
The patent applies segmentation by dividing the scheduling problem into two hierarchical levels: coarse-grained task scheduling at the apex level and fine-grained sub-task scheduling at the accelerator level. This multi-level segmentation allows the system to manage fine-grained tasks without encountering exponential scheduling complexity at a single level, as each level handles a different granularity of tasks independently
Solution Approach 2:
The patent introduces a hierarchical dimension to the scheduling problem by adding an apex level above the traditional single-level scheduler. This dimensional change transforms the problem from a two-dimensional scheduling challenge into a three-dimensional hierarchical structure, allowing fine-grained tasks to be managed through layered abstraction without exponential complexity increase
2Device complexity
If large tasks are scheduled to reduce scheduling complexity, then scheduling complexity is reduced, but memory requirements increase
Solution Approach 1:
The patent segments tasks into coarse-grained tasks for apex-level scheduling and fine-grained sub-tasks for accelerator-level execution. This segmentation allows the system to maintain lower memory requirements at each level while avoiding exponential scheduling complexity, as the apex level manages fewer large tasks and accelerators handle smaller sub-tasks with localized memory needs
3Productivity
If the number of accelerators is increased to improve performance, then computing performance is improved, but die size becomes prohibitive
Solution Approach 1:
The patent adds a hierarchical dimension to the accelerator architecture by introducing an apex level that coordinates multiple accelerators. This dimensional change allows the system to scale performance across multiple accelerators without requiring each accelerator to have proportionally larger die size, as the hierarchical structure enables efficient resource sharing and task distribution
Data Source
AI summary
Apparatus and methods are disclosed for scheduling tasks in a heterogeneous computing environment. Coarse scheduling of a received task-set is performed centrally, with tasks dispatched to respective processing resources including one or more accelerators. At each accelerator, sub-tasks of a received task are identified, scheduled, and executed. Data-transfer and computation sub-tasks can be pipelined. The accelerator operates using small tiles of local data, which are transferred to or from a large shared reservoir of main memory. Sub-task scheduling can be customized to each accelerator; coarse task scheduling can work on larger tasks; both can be efficient. Simulations demonstrate large improvements in makespan and/or circuit area. Disclosed technologies are scalable and can be implemented in varying combinations of hard-wired or software modules. These technologies are widely applicable to high-performance computing, image classification, media processing, wireless coding, encryption, and other fields.