Hierarchical Time Step Generator for Low-Jitter ADC Sampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face limitations in accurately sampling input signals in time, leading to suboptimal digitization quality.
Innovation Solution
A hierarchical time step generator is used to produce multiphase clock signals, which control a time-based analog-to-digital converter, enabling finer-grained sampling phases and increased conversion rates by employing a combination of delay-locked loops, phase-locked loops, and phase interpolation techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional single-phase clock signal is used to control the ADC, then the device complexity is low, but the sampling accuracy and conversion rate are limited
Solution Approach 1:
The clock signal generation is segmented into multiple hierarchical levels: a reference clock signal is divided into multiple first-level clock signals, which are further divided into second-level clock signals, and finally into multiple third-level multiphase clock signals. This segmentation allows the ADC to sample at multiple phases within each clock cycle, improving sampling accuracy without requiring a single excessively complex clock generation system.
Solution Approach 2:
The patent implements a nested hierarchical structure where first-level clock signals are generated from the reference clock, second-level signals are generated from first-level signals, and third-level multiphase signals are generated from second-level signals. Each level is nested within the previous level, creating a systematic approach to generating fine-grained sampling phases while managing complexity through structured organization.
2Productivity
If the sampling rate is increased to improve conversion rate, then the productivity increases, but the jitter increases and measurement precision deteriorates
Solution Approach 1:
The patent employs periodic multiphase clock signals where each phase is systematically distributed within a clock cycle. The third-level multiphase clock signals provide periodic sampling opportunities at multiple phases (e.g., 0°, 90°, 180°, 270°), allowing the system to achieve high conversion rates through parallel processing across phases while maintaining low jitter through the regular, predictable timing structure of each phase.
Data Source
AI summary
A hierarchical time step generator circuit is configured to be used for a time-based analog-to-digital converter. The hierarchical time step generator is configured to generate multiphase clock signals in response to receiving a reference clock signal. The time-based analog-to-digital converter is configured to be controlled to digitize the input signal by the multiphase clock signals. The hierarchical time step generator includes a first level time step generator configured to generate the a set of first level multiphase signals in response to receiving the reference clock signal a phase interpolator circuit configured as second level to generate second level clock signals between each of the first level clock signals and a third level configured to generate the third set of multiphase clock signals using a set of time staggered multi-phase phase locked loops synchronized to each of the second level clock signals.