Hierarchical Address Mapping for SSD Cache Efficiency
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Solution Overview
Problem
Current storage devices, such as solid state drives (SSDs), face inefficiencies in address conversion processes due to large-sized look-up tables that require significant time to read into cache memory, impacting access speed and performance.
Innovation Solution
A hierarchical look-up table (LUT) is implemented, which is structured into layers to efficiently convert logical addresses to physical addresses, with a cache memory system that stores and updates fragments of the LUT and active data map, reducing the size of data required in cache memory and enhancing access speed by using a hierarchical structure and cache lines management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large-sized look-up table is used for address conversion, then address mapping capability is improved, but read time into cache memory increases
Solution Approach 1:
The look-up table is divided into multiple layers (first layer, second layer, third layer) where each layer stores a portion of the address mapping information. The first layer contains a first plurality of entries, the second layer contains a second plurality of entries, and the third layer contains a third plurality of entries. This segmentation reduces the amount of data that needs to be read into cache memory at once, thereby reducing read time while maintaining complete address mapping capability.
Solution Approach 2:
The patent introduces a hierarchical dimension to the traditional flat look-up table structure. Instead of a single-level table, it creates a multi-layered structure where address conversion proceeds through multiple stages. Each layer processes a portion of the address bits and produces intermediate results that are combined in subsequent layers, transforming the address conversion process from a single-dimensional lookup to a multi-dimensional hierarchical process.
2Speed
If a hierarchical look-up table structure is implemented, then access speed is improved, but device complexity increases
Solution Approach 1:
The hierarchical LUT is segmented into three distinct layers, each handling a specific portion of the address conversion task. This segmentation allows the system to process address conversions in smaller, more manageable steps, improving access speed by reducing the amount of data transferred to cache memory at each step, while the modular structure helps manage complexity through clear separation of functions.
Solution Approach 2:
The patent implements a nested hierarchical structure where the second layer is nested within the context of the first layer, and the third layer is nested within the context of the second layer. Each layer contains pointers or references to the next layer, creating a nested organization where data from multiple layers is progressively combined. This nesting approach improves access speed through progressive resolution while organizing complexity in a hierarchical manner.
Data Source
AI summary
A storage device includes a nonvolatile memory, a cache memory, and a processor configured to load, from the nonvolatile memory into the cache memory, a fragment of each layer of an address mapping corresponding to a target logical address, and access the nonvolatile memory at a physical address mapped from the target logical address, by referring to the fragments of the layers of the address mapping loaded into the cache memory. The layers are arranged in a hierarchy and each layer of the address mapping except for the lowermost layer indicates correspondence between each of segmented logical address ranges mapped in the layer and a physical location of an immediately-lower layer in which said each segmented logical address range is further mapped in a narrower range. The lowermost layer indicates correspondence between each logical address mapped therein and a physical location of the nonvolatile memory associated therewith.