Hierarchical Addressing for Event-Based Neural Network Routing
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Solution Overview
Problem
Traditional neural networks in von Neumann architectures separate memory and computation, limiting their efficiency in simulating biological brain functions, and existing neuromorphic and synaptronic systems face challenges in optimizing memory and communication bandwidth.
Innovation Solution
An event-based neural network with hierarchical addressing is implemented, comprising multiple core circuits with electronic axons and neurons connected via fanout crossbars, allowing for efficient routing of event packets and reducing communication bandwidth and power requirements through programmable target axons.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional von Neumann architecture is used to separate memory and computation, then system modularity is improved, but computational efficiency for simulating biological brain functions deteriorates
Solution Approach 1:
The patent merges memory and computation into integrated core circuits where neurons and axons are physically combined. Each core circuit contains both computational elements (neurons generating event packets) and memory elements (axons receiving and storing event packets), eliminating the separation between memory and computation while maintaining modular architecture through multiple independent core circuits.
Solution Approach 2:
The patent implements a hierarchical nested structure where core circuits are organized in multiple levels. Each core circuit contains neurons and axons that are nested within a modular framework, with higher-level core circuits receiving event packets from lower-level circuits. This nesting allows efficient local computation while maintaining overall system modularity.
2Device complexity
If existing neuromorphic systems use traditional routing approaches, then implementation simplicity is improved, but memory usage and communication bandwidth requirements deteriorate
Solution Approach 1:
The patent segments the neural network into multiple core circuits, each handling specific computational tasks. Event packets are routed between these segmented circuits through a hierarchical structure, reducing the communication burden on any single circuit while distributing memory usage across multiple circuits. This segmentation decreases overall memory requirements and communication bandwidth compared to monolithic approaches.
Solution Approach 2:
The patent introduces hierarchical addressing that adds a dimensional layer to traditional routing. Instead of flat routing between neurons and axons, the system uses multi-level addressing where event packets traverse through hierarchical levels of core circuits. This dimensional change in routing architecture reduces communication bandwidth requirements by enabling more efficient packet distribution and reducing redundant transmissions.
Data Source
AI summary
The present invention provides a system comprising multiple core circuits. Each core circuit comprises multiple electronic axons for receiving event packets, multiple electronic neurons for generating event packets, and a fanout crossbar including multiple electronic synapse devices for interconnecting the neurons with the axons. The system further comprises a routing system for routing event packets between the core circuits. The routing system virtually connects each neuron with one or more programmable target axons for the neuron by routing each event packet generated by the neuron to the target axons. Each target axon for each neuron of each core circuit is an axon located on the same core circuit as, or a different core circuit than, the neuron.