Hierarchical Analog Interconnect for Mixed Voltage and Current Routing
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Solution Overview
Problem
Existing analog circuits face challenges in efficiently interconnecting multiple analog functions due to limitations in routing possibilities, parasitic capacitances, and differences in signal transfer methods, such as current-based and voltage-based signals, leading to sub-optimal performance and increased circuit overhead.
Innovation Solution
An analog circuit design that divides functions into groups with a hierarchical interconnection structure comprising local-bus and global-bus levels, allowing for both voltage and current signal transfer, utilizing local-bus hierarchy for voltage signals and global-bus hierarchy for current signals, and incorporating voltage-current converters to extend fan-in and fan-out properties and compensate for errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a switching matrix is used to interconnect analog functions, then any element can be connected with any other element without restriction, but the number of switches becomes extremely high (e.g., 100×100=10,000 switches for 100 arithmetic elements)
Solution Approach 1:
The patent divides the analog circuit into multiple clusters, where each cluster contains several arithmetic elements. This segmentation allows the interconnection structure to be broken down into smaller switching matrices (e.g., 10×10 switches per cluster instead of one large 100×100 matrix), significantly reducing the total number of switches while maintaining interconnection flexibility within and between clusters.
Solution Approach 2:
The patent introduces a hierarchical interconnection structure with two levels: intra-cluster connections and inter-cluster connections. This adds a dimensional aspect to the routing architecture, allowing signals to be routed first within a cluster and then between clusters, thereby reducing the complexity of any single switching matrix while preserving overall connectivity.
2Adaptability or versatility
If a switching matrix with many switches is used, then interconnection flexibility is maintained, but parasitic capacitances in the signal lines and switches increase
Solution Approach 1:
By segmenting the circuit into clusters with smaller switching matrices, the patent reduces the number of switches and signal lines in each matrix, thereby reducing the total parasitic capacitance. The hierarchical structure ensures that parasitic effects are localized to smaller regions rather than accumulating across a large global matrix.
Solution Approach 2:
The patent introduces cluster-level interconnection structures as intermediaries between arithmetic elements and global routing. These intermediate structures reduce the need for long signal lines and reduce the number of switches required for direct global connections, thereby reducing parasitic capacitances while maintaining interconnection flexibility.
3Device complexity
If multiple stages are used in the switching matrix to reduce the number of switches, then the number of switches is reduced, but signal bandwidth is reduced due to parasitic capacitances and on-resistances
Solution Approach 1:
The patent uses segmentation to create smaller switching matrices that require fewer switches, thereby reducing total parasitic capacitance and on-resistance in the signal path. This allows for faster signal traversal compared to multi-stage larger matrices, as the signal passes through fewer switching elements in each cluster.
Solution Approach 2:
The hierarchical structure allows signals to be routed efficiently within clusters (first dimension) and between clusters (second dimension), reducing the need for multiple serial switching stages. This dimensional approach maintains signal bandwidth by minimizing the number of switches in series that a signal must pass through.
4Area of stationary object
If local and global routing is used in FPGA, then area used for signal lines is reduced and signal transfer effort is optimized, but the approach is based on digital logic blocks and switching mechanisms
Solution Approach 1:
The patent creates a universal interconnection architecture that can serve both digital and analog functions. The hierarchical routing structure with local and global levels is designed to be function-agnostic, allowing it to interconnect various types of arithmetic elements (adders, multipliers, integrators) regardless of whether they are digital or analog, thereby achieving universality.
Solution Approach 2:
The patent adapts the routing parameters and characteristics to suit analog functions while maintaining the local-global hierarchy. This includes optimizing signal line lengths, minimizing parasitic effects, and adjusting switching characteristics to preserve signal integrity for analog applications, thereby making the architecture versatile across different function types.
Data Source
AI summary
There is provided an analog circuit comprising: a plurality of analog functions, which are divided into at least two groups of analog functions, and an interconnection structure configured to interconnect the plurality of analog functions so as to enable transfer of both voltage and current signals between analog functions among the plurality of analog functions. The interconnection structure comprises at least two hierarchy levels of interconnections, wherein a local-bus hierarchy level is configured to interconnect analog functions of a respective group, and a global-bus hierarchy level is configured to interconnect analog functions of the plurality of groups. The local-bus hierarchy level comprises voltage signal lines for transferring voltage signals and/or current signal lines for transferring current signals, and the global-bus hierarchy level comprises voltage signal lines for transferring voltage signals and/or current signal lines for transferring current signals.