Hierarchical Arbitration Logic for FPGA Performance
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Solution Overview
Problem
Current arbitration schemes in field programmable gate arrays (FPGAs) consume significant programmable logic and are often on the critical path, limiting the ability to achieve improved system-on-chip design performance due to their non-hierarchical and inefficient nature.
Innovation Solution
Implementing a hierarchical arbitration method that uses multiple levels of arbitration blocks and multiplexers to arbitrate and multiplex master requests and payloads, reducing the critical path and programmable logic area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional arbitration schemes are used in FPGAs, then arbitration functionality is provided, but the maximum operating frequency (fmax) is limited and significant programmable logic area is consumed
Solution Approach 1:
The arbitration logic is divided into multiple hierarchical levels, where each level handles a subset of masters. First-level arbitration blocks arbitrate between pairs of masters, second-level blocks arbitrate between first-level blocks, and so on. This segmentation reduces the complexity of any single arbitration block and shortens the critical path, thereby improving maximum operating frequency while distributing the programmable logic usage across multiple smaller units.
2Productivity
If traditional non-hierarchical arbitration schemes are used, then arbitration is provided, but the arbitration logic lies on the critical path causing performance bottlenecks
Solution Approach 1:
The arbitration process is segmented into multiple hierarchical levels executed in sequence. Instead of a single monolithic arbitration block that creates a long critical path, the system uses first-level arbitration blocks that resolve conflicts among subsets of masters, then second-level blocks that resolve conflicts among the winners from first level, and so on. This segmentation breaks the critical path into shorter segments, reducing overall arbitration delay and improving system performance.
Solution Approach 2:
The hierarchical arbitration structure performs preliminary arbitration at lower levels before proceeding to higher levels. First-level arbitration blocks perform preliminary conflict resolution among master subsets, eliminating many potential conflicts before they reach higher levels. This preliminary action reduces the workload and delay at higher arbitration levels, effectively shortening the overall critical path.
3Reliability
If traditional arbitration schemes are used, then master access control is provided, but the arbitration logic consumes significant portion of FPGA programmable logic
Solution Approach 1:
The arbitration functionality is segmented into multiple small arbitration blocks distributed across hierarchical levels. Each arbitration block handles a limited subset of masters or intermediate results, requiring significantly less logic resources per block compared to a single monolithic arbitration block. This segmentation maintains complete arbitration functionality while dramatically reducing the concentrated programmable logic area usage.
Solution Approach 2:
The arbitration structure transitions from a single-dimensional flat architecture to a multi-dimensional hierarchical architecture. By adding the hierarchical dimension, the system distributes arbitration logic across multiple levels rather than concentrating it in one layer, effectively reducing the area footprint at any single level while preserving overall arbitration capability.
Data Source
AI summary
Systems and methods for increasing speed and reducing area for arbitration logic in an integrated circuit (IC) are provided. For example, in one embodiment, a method includes arbitrating at least one master request in a first level of arbitration blocks. A second level of arbitration blocks arbitrates at least two arbitration blocks from the first level. A first level of multiplexers multiplex at least one master payload based at least in part upon the arbitration of the first level of arbitration blocks. A second level of multiplexers multiplex at least two signals propagated from the first level of multiplexers.