Hierarchical Barrier Synchronization Register for Multi-Node Systems
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Solution Overview
Problem
Existing synchronization methods in multiprocessor systems incur high latency and overhead due to asymmetric software implementation and the need for processors to poll barrier synchronization registers, leading to energy inefficiency and long synchronization times.
Innovation Solution
A hierarchical barrier synchronization method that uses a register with electrically tied bits to determine when all processor threads have reached a synchronization point, allowing for symmetric software implementation and efficient communication of synchronization signals within and across chips, reducing the need for polling and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processors poll barrier synchronization registers to determine synchronization status, then synchronization can be achieved, but latency increases and energy consumption rises
Solution Approach 1:
The patent replaces the software-based polling mechanism with a hardware-based automatic notification system. Each processor core has a barrier synchronization register bit that is automatically cleared by hardware when the barrier is reached, eliminating the need for continuous software polling and reducing both latency and energy consumption while maintaining synchronization accuracy
Solution Approach 2:
The barrier synchronization mechanism becomes self-service through automatic hardware detection and notification. The system automatically detects when all processors have reached the barrier point and notifies them without requiring active polling, making the synchronization process autonomous and efficient
2Reliability
If asymmetric software implementation is used for barrier synchronization, then synchronization can be coordinated, but overhead increases and scalability decreases
Solution Approach 1:
The patent introduces asymmetry at the hardware level rather than software level. The barrier synchronization register bits are implemented with asymmetric hardware logic that automatically detects when all processors have reached the barrier, allowing symmetric software implementation while maintaining reliable synchronization coordination
Solution Approach 2:
The patent substitutes complex asymmetric software coordination logic with simple hardware-based automatic detection and notification mechanisms. The barrier synchronization register and associated hardware logic automatically handle the coordination complexity, reducing software overhead and improving scalability
3Reliability
If processors continuously poll barrier registers, then synchronization status can be monitored, but energy consumption increases
Solution Approach 1:
The patent replaces energy-intensive continuous software polling with a hardware-based automatic notification system. The barrier synchronization register bits are automatically cleared by hardware logic when the barrier is reached, and processors are notified without active consumption of processing energy, maintaining reliable monitoring while dramatically reducing energy usage
4Adaptability or versatility
If on-chip synchronization is implemented without dedicated hardware features, then software flexibility is maintained, but synchronization latency increases
Solution Approach 1:
The patent substitutes software-based synchronization timing with hardware-based automatic barrier detection and notification. The barrier synchronization register and hardware logic automatically detect when all processors have reached the barrier and notify them immediately, reducing on-chip synchronization latency while maintaining software flexibility through the register interface
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves low-latency, low-overhead synchronization by eliminating the need for processor polling and enabling efficient propagation of synchronization signals, resulting in a more energy-efficient and scalable synchronization mechanism across multiprocessor systems.
Implementation Method 1
determining whether all of the plurality of threads reached the barrier by electrically tying bits of the register together and 'AND'ing the input bit signals (AND is a Boolean logic function)
Data Source
AI summary
A hierarchical barrier synchronization of cores and nodes on a multiprocessor system, in one aspect, may include providing by each of a plurality of threads on a chip, input bit signal to a respective bit in a register, in response to reaching a barrier; determining whether all of the plurality of threads reached the barrier by electrically tying bits of the register together and “AND”ing the input bit signals; determining whether only on-chip synchronization is needed or whether inter-node synchronization is needed; in response to determining that all of the plurality of threads on the chip reached the barrier, notifying the plurality of threads on the chip, if it is determined that only on-chip synchronization is needed; and after all of the plurality of threads on the chip reached the barrier, communicating the synchronization signal to outside of the chip, if it is determined that inter-node synchronization is needed.