Hierarchical Bit Line Structure for Semiconductor Memory
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Solution Overview
Problem
Conventional hierarchical memory cell arrays face challenges in achieving a configuration that utilizes both differential type sense amplifiers and single-ended global bit lines, which is desirable for sufficient signal amplification while also considering manufacturing process restrictions.
Innovation Solution
A semiconductor device configuration that includes local bit lines, differential type local sense amplifiers, a global bit line, and switches controlling electrical connections between local and global bit lines, allowing for the use of both differential and single-ended configurations to amplify signal voltages effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If differential type local sense amplifiers are used to amplify minute signal voltage, then sensing margin is improved, but device complexity increases due to the need for additional switch transistors in the write data path
Solution Approach 1:
The patent extracts the write switch function from the local sense amplifier circuit by introducing a separate write switch transistor (TW) positioned between the write data line and the local bit lines. This separation removes the complexity of controlling write operations within the sense amplifier, allowing the differential local sense amplifier to focus solely on amplification while write operations are managed independently by the extracted write switch.
Solution Approach 2:
The patent introduces an intermediary write switch transistor (TW) that mediates between the write data line and the local bit lines. This intermediary component enables independent control of write operations without interfering with the differential sense amplifier's amplification function, thus improving sensing margin while managing device complexity through functional separation.
2Ease of manufacture
If single-ended global bit line configuration is used to widen line pitch, then ease of manufacture is improved, but signal amplification capability deteriorates compared to differential configuration
Solution Approach 1:
The patent segments the bit line hierarchy into differential local bit lines (for high-gain amplification near memory cells) and single-ended global bit lines (for simplified wiring and manufacturing). This segmentation allows each level to be optimized for its specific function: local bit lines provide differential signaling for sensing margin, while global bit lines provide manufacturing ease with wider pitch.
Solution Approach 2:
The patent applies different signaling configurations to different spatial levels of the bit line hierarchy. At the local level (near memory cells), differential configuration is used to maximize sensing margin. At the global level (upper hierarchy), single-ended configuration is used to simplify manufacturing and widen line pitch. This local quality differentiation resolves the contradiction between amplification capability and ease of manufacture.
Data Source
AI summary
A semiconductor device is disclosed which comprises first and second local bit lines coupled to a plurality of memory cells arranged in first and second areas, respectively, a differential type local sense amplifier amplifying a voltage difference between the first and second local bit lines, a global bit line arranged in an extending direction of the first and second local bit lines, and first and second switches controlling electrical connections between the first and second local bit lines and the global bit line, respectively.