Hierarchical Bit Line Semiconductor Memory High-Speed Low-Voltage Read
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Solution Overview
Problem
Conventional semiconductor memory devices with hierarchical bit line structures face challenges in performing high-speed read operations at low voltages due to the substrate bias effect, which reduces the current drive capability of transistors, and require additional production steps or circuitry to mitigate these issues, increasing manufacturing costs.
Innovation Solution
A semiconductor memory device with a hierarchical bit line structure that eliminates the need for transistors connecting the main and sub-bit lines, utilizing a voltage control section with specific MOS transistors to manage voltage and current drive capabilities, allowing for high-speed read operations with low power source voltages without the substrate bias effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transistors are used to connect main bit lines and sub-bit lines in conventional hierarchical bit line structures, then voltage control and current drive capability are achieved, but the substrate bias effect reduces transistor performance and requires additional production steps or circuitry, increasing manufacturing costs
Solution Approach 1:
The patent removes the block select transistor that connects main bit lines to sub-bit lines from the conventional hierarchical bit line structure. By extracting this transistor component, the patent eliminates the substrate bias effect that degraded transistor performance, while maintaining voltage control through alternative means (voltage control section with MOS transistors). This reduction in component complexity lowers manufacturing costs and simplifies production processes.
Solution Approach 2:
The patent changes the voltage control mechanism from traditional transistor-based switching to a voltage control section that applies power source voltages directly to specific nodes (main bit lines and sub-bit lines). This parameter change in the control approach eliminates the need for substrate bias compensation circuits and specialized production steps, thereby reducing manufacturing costs while maintaining current drive capability.
2Power
If transistors connect main bit lines and sub-bit lines in conventional hierarchical bit line structures, then voltage control is achieved, but the device area increases due to additional transistors and circuits required to mitigate substrate bias effects
Solution Approach 1:
The patent extracts and removes the block select transistor and associated circuitry from the conventional hierarchical bit line structure. By taking out these components that caused substrate bias effects, the patent reduces the overall device area while maintaining voltage control functionality through a more compact voltage control section.
Solution Approach 2:
The patent merges the voltage control function into an integrated voltage control section that works in conjunction with the existing MOS transistors in the memory cell array. This merging approach eliminates the need for separate, dedicated voltage control circuits and transistors, thereby reducing device area while maintaining effective voltage control.
3Productivity
If conventional hierarchical bit line structures with transistors are used, then read operations can be performed, but high-speed read operations at low voltages are hindered by the substrate bias effect
Solution Approach 1:
The patent removes the block select transistor that created substrate bias effects, thereby eliminating the reliability issue that hindered high-speed read operations at low voltages. With this extraction, the remaining MOS transistors operate without substrate bias degradation, enabling high-speed read operations even at reduced voltage levels.
Solution Approach 2:
The patent converts the harmful substrate bias effect into a beneficial design decision by removing the transistor configuration that caused it. The voltage control section then applies power source voltages in a way that actually improves transistor performance by eliminating the negative substrate bias, turning a potential harm into a benefit for high-speed operation.
Data Source
AI summary
A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarray 12 includes a first MOS transistor PD1 for charging a main bit line MBL1 and a second MOS transistor PS1 for charging a sub-bit line SBL1—1. The source electrode of the second MOS transistor PS1 is connected to a power source voltage, and the source electrode of the first MOS transistor PD1 is connected via a fourth MOS transistor PD2 to the power source voltage. Since there is not a resistance between the main bit line MBL1 and the sub-bit line SBL1—1, which is present if a transistor is used to achieve conduction therebetween, discharging of the main bit line and charging of the sub-bit line can be performed with high speed.