Hierarchical Bit Line Refresh Circuit for Semiconductor Memory
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Solution Overview
Problem
In semiconductor memory devices with hierarchical bit line structures, the refresh operation consumes a significant amount of current due to the involvement of both local and global bit lines and sense amplifiers, and the existing techniques to reduce the number of global sense amplifiers lead to data destruction in unconnected local bit lines.
Innovation Solution
A semiconductor device with a memory cell array that includes a local bit line, a global bit line, and a bit line control circuit with a restoring circuit that isolates the local and global bit lines during refresh operations, allowing data to be refreshed without using the global bit lines and sense amplifiers, while maintaining electrical connectivity for read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If both local bit line and global bit line are used in refresh operation, then data can be restored through hierarchical structure, but consumption current increases significantly
Solution Approach 1:
The bit line structure is segmented into local bit lines (LBL) and global bit lines (GBL), with the refresh operation using only the local bit line segment. This segmentation allows the refresh function to be performed independently without involving the global bit line, thereby reducing current consumption while maintaining data restoration capability.
Solution Approach 2:
The global bit line and global sense amplifier are extracted (removed) from the refresh operation path. By taking out these components from the refresh signal path and using only the local bit line with local sense amplifier for refresh, the invention eliminates the large current consumption associated with global bit line charging/discharging while preserving the hierarchical structure for read/write operations.
2Length of stationary object
If local sense amplifier is added to restore data without global bit line, then wiring pitch of global bit line can be broadened, but chip area increases
Solution Approach 1:
The local sense amplifier is designed with local quality - it has full functionality for read/write operations (including restore function) but is selectively activated. During refresh, only the restore function is used with local bit line, while during read/write, the amplifier connects to global bit line. This local quality allows flexible area utilization without requiring additional global sense amplifiers.
Solution Approach 2:
The local sense amplifier is designed with multi-functionality to perform both sense amplification and data restoration functions. This universal design allows the same circuit structure to serve multiple purposes: restoring data during refresh operations on local bit lines and sensing data during read operations on global bit lines, thereby eliminating the need for separate restoration circuits and reducing overall chip area.
3Device complexity
If local bit line is not connected to global sense amplifier, then global sense amplifier count is reduced, but data on unconnected local bit line is destroyed
Solution Approach 1:
The local sense amplifier performs preliminary restoration action on data from the local bit line before any potential connection to global bit line. By restoring the data locally first, the invention ensures data integrity is maintained even when the local bit line is not connected to the global sense amplifier, preventing data destruction while still allowing reduction in global sense amplifier count.
Data Source
AI summary
Disclosed herein is a semiconductor device comprising a memory cell, a local bit line coupled to the memory cell, a global bit line provided correspondingly to the local bit line, and a bit line control circuit coupled between the local bit line and the global bit line. The bit line control circuit includes a restoring circuit that is activated in a refresh mode to refresh data of the memory cell while being in electrical isolation from the global bit line.