Hierarchical Bit Line Scheme for DRAM Power and Speed
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Solution Overview
Problem
Current semiconductor memory devices, such as DRAM, face challenges in increasing memory capacity, speed, and reducing power consumption while maintaining data integrity, particularly in implementing a hierarchical bit line scheme effectively.
Innovation Solution
A semiconductor memory device is designed with a hierarchical bit line scheme where a bit line is separated from a global bit line, utilizing sense amplifiers and transistors to drive and sense voltage levels, and incorporating parity cells to determine data validity during operations, with selective power supply lines and separate precharge and restoration operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a hierarchical bit line scheme is implemented to increase memory capacity and speed, then memory capacity and speed are improved, but power consumption increases and data integrity becomes harder to maintain
Solution Approach 1:
The bit line system is segmented into local bit lines (BL0-BL7) and global bit lines (GBL0-GBL7), with sense amplifiers (SA0-SA7) positioned at intermediate stages. This hierarchical segmentation allows memory cells to be accessed through local bit lines first, then selectively amplified to global bit lines, reducing the power consumption associated with charging and discharging entire global bit line networks while maintaining high memory capacity and access speed.
2Productivity
If a hierarchical bit line scheme is implemented to increase memory capacity and speed, then memory capacity and speed are improved, but data integrity becomes harder to maintain
Solution Approach 1:
Sense amplifiers (SA0-SA7) serve as intermediary devices between local bit lines and global bit lines. These sense amplifiers detect voltage levels on local bit lines, amplify the signals, and drive the global bit lines to predetermined voltage levels. This intermediary function ensures that data integrity is maintained during the hierarchical signal transmission, preventing signal degradation and ensuring accurate data representation throughout the memory system.
3Use of energy by moving object
If bit line is separated from global bit line with sense amplifiers, then power consumption is reduced and data integrity is improved, but device complexity increases
Solution Approach 1:
The sense amplifiers (SA0-SA7) are designed with multi-functionality to justify their inclusion in the hierarchical bit line system. Each sense amplifier performs multiple functions: detecting voltage levels on local bit lines, amplifying weak signals, driving global bit lines to predetermined voltage levels, and maintaining data integrity during transitions. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby minimizing the increase in device complexity while achieving power consumption reduction and data integrity improvement.
Data Source
AI summary
A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.