Hierarchical Block Diagram Generation for Electronic Circuit Design
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Solution Overview
Problem
Graphical representations of electronic circuit designs often obscure high-level design information due to the inclusion of low-level details, making it difficult to trace connections between functional blocks in complex designs with many interconnects.
Innovation Solution
A processor-based method that generates a block diagram from textual design specifications by identifying and diagrammatically representing multi-master buses, bus masters, bus slaves, and input/output ports, while omitting selected low-level details to focus on a bus-centric and processor-centric view, using Scalable Vector Graphics (SVG) and Joint Picture Experts Group (JPEG) formats.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If a graphical representation includes all low-level implementation details, then completeness of design information is improved, but readability and ease of understanding deteriorates due to excessive interconnects obscuring high-level design information
Solution Approach 1:
The graphical representation is segmented into multiple hierarchical levels. The first level shows high-level functional blocks with simplified interconnections, while lower levels reveal progressively more detailed implementation information. This segmentation allows users to view the design at the appropriate level of abstraction without being overwhelmed by all details simultaneously.
Solution Approach 2:
The patent introduces a hierarchical dimension to the graphical representation. Instead of presenting all information in a single flat view, the design is organized across multiple hierarchical levels, allowing navigation between abstract high-level views and detailed low-level views. This dimensional approach resolves the contradiction by providing both completeness and readability through selective viewing.
2Manufacturing precision
If a graphical representation shows detailed interconnections between all components, then accuracy of design specification is improved, but complexity of the diagram increases making it difficult to trace basic connections
Solution Approach 1:
The diagram complexity is managed through segmentation into hierarchical levels. Each level segments the design information appropriately, showing only the interconnections relevant to that level of abstraction. This maintains accuracy by preserving all connection information across levels while reducing perceived complexity at any single viewing level.
Solution Approach 2:
The graphical representation is made dynamic through interactive navigation between hierarchical levels. Users can dynamically expand or collapse detail levels, transitioning between simplified views and detailed views as needed. This dynamic capability allows the diagram to adapt its complexity based on the user's information needs.
3Measurement precision
If textual design specifications are used, then precision of design description is improved, but ease of verification and communication deteriorates compared to graphical representations
Solution Approach 1:
The patent merges the advantages of both textual and graphical representations. The system automatically generates hierarchical graphical representations from textual design specifications, combining the precision of text-based descriptions with the visual clarity of graphical displays. This merging allows verification and communication benefits of graphics while maintaining the precision of textual specifications.
Solution Approach 2:
The system creates a graphical copy or visualization of the textual design specification. By automatically generating hierarchical diagrams from the text, the invention provides a visual copy that preserves the precision of the original textual description while adding the communication and verification advantages of graphical representation.
Data Source
AI summary
Method and apparatus are described for generating a block diagram of an electronic circuit design. In one embodiment, each instance of a multi-master bus, a bus master of a multi-master bus, a bus slave of a multi-master bus, a memory, a co-processor and an input/output port is are identified. Instances of input/output ports are placed about a perimeter of a first area of the diagram. Each instance of a multi-master bus is placed in a bus area within the first area and each bus master is placed in a master area. The bus slaves of a bus are collected in a group, and the group is placed as a single block in a slave area within the first area. The group of bus slave slaves is aligned with a bus master. A diagrammatic representation is output consistent with the placement representations.