Hierarchical Buffering for Phase Change Memory Resistivity Drift
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Solution Overview
Problem
Phase change memory devices face challenges in accurately reading data due to the rapid resistivity drift of phase change memory cells immediately after writing, leading to increased bit error rates and prolonged read times, as the distribution of transition latencies makes it difficult to ascertain clear read/demarcation voltages.
Innovation Solution
Implementing a set of hierarchical data structures that buffer user data and parity bits during the initial period of high resistivity drift, allowing for error correction and efficient read operations as the cells transition from a crystalline to an amorphous phase, and subsequently relying on parity bits stored within the memory cells for stable read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If reads are performed immediately after write operations in phase change memory, then read speed is improved, but bit error rate increases due to rapid resistivity drift
Solution Approach 1:
The patent applies preliminary action by performing a read verification operation immediately after the write operation, before the actual read request is serviced. This preliminary read detects bit errors caused by resistivity drift during the settling phase, allowing for error correction or retry operations before the data is used, thus maintaining both fast read speed and high reliability
Solution Approach 2:
The patent implements feedback by using the results of the preliminary read operation to determine whether the main read operation should proceed, be retried, or require error correction. This feedback mechanism allows the system to adapt to the resistivity drift condition and make informed decisions about data integrity, resolving the contradiction between speed and reliability
2Reliability
If read/demarcation voltages are set to accommodate the tails/ends of transition latency distribution, then bit error rate is reduced, but read times are lengthened
Solution Approach 1:
The patent performs a preliminary read operation with optimized demarcation voltages immediately after writing, before servicing the actual read request. This preliminary action allows the system to use conservative voltage settings that ensure accuracy without impacting the timing of the main read operation, thus reducing bit errors while maintaining fast read times
Solution Approach 2:
The patent creates a copy of the data by performing a preliminary read operation that reads the data again after the write operation. This copy is used to verify data integrity and detect bit errors caused by resistivity drift, allowing the main read operation to proceed with confidence without needing to use conservative voltage settings that would slow it down
3Reliability
If hierarchical buffering is implemented to buffer user data and parity bits during high drift period, then bit error rate is reduced, but device complexity increases
Solution Approach 1:
The patent segments the error correction function into two parts: a preliminary read operation that detects errors caused by resistivity drift, and a main read operation that services the actual request. This segmentation allows error detection and correction to be performed separately without requiring complex buffering structures, maintaining simplicity while improving reliability
Solution Approach 2:
The patent makes the error detection and correction process self-service by using the preliminary read operation to automatically detect and flag bit errors before the main read operation. This self-service mechanism eliminates the need for complex external buffering or error management structures, as the system handles error correction autonomously through the preliminary action
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces bit error rates and maintains efficiency in reading user data from phase change media by utilizing buffered parity bits during the high drift period and direct reading from memory cells once stability is achieved, thereby improving read accuracy and reducing read times.
Implementation Method 1
the rapid resistivity drift of phase change memory cells immediately after writing, leading to increased bit error rates
Data Source
AI summary
A computer-implemented method for writing data to a first media using a set of data structures to reduce potential errors when reading the data from the first media is described. The method includes writing, user data to a set of memory cells in the first media; and storing, in response to writing the user data to the set of memory cells, a first set of parity bits associated with the user data in a first buffer that is held within a second media separate from the first media and is a different type than the first media, wherein the first set of parity bits provide error correction information for correcting errors introduced to the user data while stored in the set of memory cells or read from the set of memory cells.