Hierarchical Bus Control Circuit for Priority Arbitration
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Solution Overview
Problem
In large-scale hardware systems with multiple bus master modules, existing bus systems face issues with wiring congestion and limited operating frequency due to the complexity of logic circuits and arbitration in shared and hierarchical bus systems, leading to potential misordering of bus transfers based on priority.
Innovation Solution
A bus control circuit is designed to manage bus transfers in a hierarchical bus method by using a path encoding circuit and MUX control circuit to selectively route bus transfer signals based on arbitration results, ensuring priority-based ordering through a simplified logic that reduces circuit scale and wiring congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single bus switch is used to select one access from multiple bus master modules, then arbitration can be performed based on predetermined priority, but wiring congestion occurs and circuit scale becomes large
Solution Approach 1:
The patent divides the single bus switch into multiple stages of bus switches arranged hierarchically. The first-stage bus switches receive access requests from multiple bus master modules and perform preliminary arbitration, while the second-stage bus switch performs final arbitration. This segmentation reduces the number of inputs each individual switch must handle, thereby reducing wiring congestion and circuit scale while maintaining priority-based arbitration capability.
2Reliability
If a single bus switch is used to select one access from multiple bus master modules, then arbitration can be performed, but the number of logic stages increases and operating frequency is limited
Solution Approach 1:
The patent segments the arbitration function across multiple stages with reduced logic depth at each stage. Each bus switch stage performs a subset of the total arbitration logic, reducing the critical path delay compared to a single large-scale bus switch. This enables higher operating frequency while maintaining the complete arbitration function.
3Device complexity
If hierarchical bus system with multiple stages is used, then wiring congestion is reduced, but priority orders may differ between stages and bus transfer ordering may be incorrect
Solution Approach 1:
The patent employs feedback mechanisms where arbitration results from the first-stage bus switches are fed back to the second-stage bus switch for final arbitration. This feedback loop ensures that the hierarchical structure maintains consistency with the predetermined priority orders, preventing misordering of bus transfers while still benefiting from reduced wiring congestion at each stage.
Data Source
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AI summary
A bus control circuit comprises an arbitration circuit which receives a bus-transfer request from each of a plurality of bus masters and outputs an arbitration result signal, in accordance with a priority order, to one of the bus masters, and a plurality of bus switches, wherein each bus switch comprises a selection circuit which includes a plurality of input terminals for receiving a plurality of bus transfer signals and an output terminal for transmitting one bus transfer signal to a downstream side, and a control circuit which receives the arbitration result signal from the arbitration circuit and controls the selection circuit based on the arbitration result signal to select one of the plurality of input terminals, and a slave module is connected to the output terminal of the selection circuit in the bus switch located at a most downstream position.