Hierarchical Cache Error Correction for Multi-Bit Data Recovery
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Solution Overview
Problem
Electronic devices face data errors due to environmental variations and hardware failures, which existing error control modules struggle to efficiently detect and correct, especially in multi-bit errors.
Innovation Solution
A two-stage error correction method using in-line error detection information and residual sums calculated over finite fields, allowing for efficient correction of single and multi-bit errors with reduced circuit area, employing SEC-DED and DEC-TED bits for error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error control modules are used to detect and correct data errors, then error detection capability is provided, but circuit area increases and multi-bit error correction efficiency decreases
Solution Approach 1:
The patent divides error correction into two hierarchical stages: first-stage SEC-DED correctors handle single-bit errors at each data segment level, while second-stage DEC-TED correctors handle double-bit errors at the cache line level. This segmentation allows comprehensive error correction coverage while optimizing circuit area by distributing correction logic across different hierarchical levels rather than implementing a single complex correction system.
2Reliability
If comprehensive error correction is implemented for all bit errors, then reliability improves, but circuit complexity and area increase significantly
Solution Approach 1:
The error correction system is segmented into hierarchical levels with different correction capabilities. First-stage correctors use simple SEC-DED logic for single-bit errors, while second-stage correctors use DEC-TED logic for double-bit errors. This segmentation enables comprehensive error correction without requiring a single overly complex correction system, thereby reducing overall circuit complexity while maintaining high reliability.
Solution Approach 2:
The patent implements partial error correction at each hierarchical stage rather than attempting to correct all possible errors in a single pass. The first stage corrects single-bit errors, and the second stage corrects remaining double-bit errors. This staged approach provides sufficient error correction capability for practical applications while keeping circuit complexity manageable by not implementing excessive correction capability at each individual stage.
Data Source
AI summary
A data processing device can perform error detection and correction in two stages: in the first stage, error detection is performed for the load data using the in-line error detection information. If a first type of error is detected in the data segment, the error is corrected using the in-line error detection information. If a second type of error is detected error correction is performed using the residual sum.