Hierarchical Cache Memory System with Non-Volatile TLB
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Solution Overview
Problem
The increasing capacity of cache memories leads to longer determination times, which in turn increases access times to main memory, thereby decreasing processor processing capability due to the time required for tag information management and address conversion processes.
Innovation Solution
A cache memory system is implemented with a first cache memory for storing data by address, a second cache memory using non-volatile memory cells with higher speed and larger capacity than main memory, and a translation lookaside buffer (TLB) that stores address conversion information and flag information per page, allowing for reduced search delays through a hierarchical structure and set associative configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cache memory capacity is increased, then data storage capability is improved, but determination time for tag information increases
Solution Approach 1:
The cache memory is divided into multiple levels (first cache memory and second cache memory), with each level having different capacities and access characteristics. The tag information is segmented and stored across these levels, allowing the system to benefit from both small fast cache and large capacity cache without proportionally increasing determination time.
Solution Approach 2:
The patent introduces a hierarchical cache structure that adds a temporal and spatial dimension to cache organization. By arranging cache memories in levels with different access speeds and capacities, the system resolves the contradiction between capacity and access time through multi-dimensional optimization rather than single-dimensional scaling.
2Quantity of substance
If tag information size increases, then cache memory capacity is improved, but access speed to main memory decreases
Solution Approach 1:
Tag information is segmented and distributed across multiple cache levels. The first cache memory holds frequently accessed tag information for fast access, while the second cache memory (non-volatile) stores larger amounts of tag information. This segmentation allows main memory access speed to be maintained for hot data while providing large capacity for cold data.
Solution Approach 2:
The first cache memory acts as an intermediary between the processor and the second cache memory/main memory. It buffers access to tag information, providing fast access paths for frequently used tags while allowing slower access to the larger second cache without directly impacting processor performance.
3Quantity of substance
If determination process time increases, then cache capacity is improved, but processor processing capability decreases
Solution Approach 1:
The determination process is segmented across multiple cache levels. Common tags are resolved in the fast first cache memory, preventing processor stalls. Less frequently accessed tags are handled by the second cache memory, which has larger capacity but slower access. This segmentation ensures that the majority of determination processes complete quickly, maintaining processor productivity.
Solution Approach 2:
Tag information is pre-loaded and organized in the first cache memory based on access patterns. By preparing frequently accessed tag information in advance in the fast cache, the system eliminates processor waiting time for determination processes, thereby maintaining high processing capability while supporting large overall cache capacity.
Data Source
AI summary
A cache memory system has a first cache memory comprising one or more levels, to store data corresponding to addresses, a second cache memory comprising a plurality of non-volatile memory cells, which has higher speed capability than a main memory, has a larger capacity than the first cache memory and stores data corresponding to addresses, and a first storage to store address conversion information from a virtual address issued by a processor to a physical address and to store flag information indicating whether data is stored in the second cache memory by a page having a larger data amount than a cache line, the first cache memory being accessed by the cache line.