Hierarchical Cache Allocation Using Range-Aware Memory Requests
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Solution Overview
Problem
Existing electronic devices face challenges in efficiently allocating data to multiple caches due to differences in access speed and capacity, leading to suboptimal performance.
Innovation Solution
An electronic device that allocates data to multiple caches based on cache allocation range information, determining operations based on the characteristics of each cache level, including a main memory, multiple caches hierarchically connected, and processing circuitry to manage memory requests with cache allocation range information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is allocated to caches closer to the processor, then access speed is improved, but storage capacity is reduced
Solution Approach 1:
The patent segments the cache system into multiple hierarchical levels (L1, L2, L3 caches), where each level serves different storage capacity and access speed requirements. This segmentation allows the system to simultaneously provide fast access for frequently used data and large storage capacity for less frequently accessed data, resolving the contradiction between speed and capacity.
Solution Approach 2:
The patent introduces a hierarchical dimension to the cache structure, organizing caches in multiple levels rather than a single flat structure. This dimensional change enables the system to balance speed and capacity by placing different types of data at different hierarchical levels, with higher levels providing fast access and lower levels providing larger capacity.
2Quantity of substance
If data is allocated to caches farther from the main memory, then storage capacity is increased, but access speed is reduced
Solution Approach 1:
The patent segments the cache system into multiple hierarchical levels, with lower levels (L3, L4) providing larger storage capacity and higher levels (L1, L2) providing faster access. This segmentation allows the system to allocate data to appropriate cache levels based on access frequency and capacity requirements, resolving the contradiction between capacity and speed.
Solution Approach 2:
The patent implements a nested cache hierarchy where smaller, faster caches are nested within larger, slower caches (L1 within L2, L2 within L3, etc.). This nesting structure allows the system to provide fast access for frequently accessed data in upper levels while maintaining large capacity in lower levels, effectively resolving the speed-capacity tradeoff.
3Productivity
If cache allocation is performed without cache allocation range information, then device complexity is reduced, but cache performance is suboptimal
Solution Approach 1:
The patent performs preliminary action by including cache allocation range information in memory requests before data access operations. This allows caches to pre-determine whether they can service requests based on allocation ranges, improving cache performance through better data placement decisions without significantly increasing device complexity, as the information is carried along with existing memory requests.
Data Source
AI summary
An electronic device including a main memory, a plurality of caches that are hierarchically connected, the plurality of caches configured to store part of data stored in the main memory, and processing circuitry configured to transmit a memory request for desired data to the plurality of caches and the main memory, the memory request including cache allocation range information associated with the desired data, and each of the plurality of caches are configured to, determine whether to perform an operation corresponding to the memory request based on the cache allocation range information.