Hierarchical Clock Domain Crossing Verification for Electronic Design
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Solution Overview
Problem
Conventional methods for identifying and fixing clock domain crossing (CDC) errors in electronic designs are costly and computationally intensive, requiring elaborate analysis of entire designs, which modern computing systems often cannot handle due to their size and complexity.
Innovation Solution
The implementation of hierarchical clock domain crossing verification techniques, which decompose electronic designs into top hierarchies and child blocks, allowing separate processing on computing nodes to identify and integrate clock domain crossing structures without elaborating the entire design, thereby reducing computational burden.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional approaches elaborate and analyze the entire electronic design to identify CDC violations, then comprehensive verification is achieved, but computational resources become prohibitively excessive and processing time increases significantly
Solution Approach 1:
The patent divides the electronic design into hierarchical levels (top hierarchy, child hierarchies, and individual blocks). The verification process is segmented to operate at different levels: first identifying CDC structures at the top hierarchy level without full elaboration, then selectively elaborating only those blocks that contain potential CDC violations. This segmentation allows comprehensive verification while reducing computational resources by avoiding elaboration of the entire design.
2Measurement precision
If the entire electronic design is elaborated to generate a netlist model for CDC analysis, then accurate identification of CDC structures is achieved, but processing time and computational burden become unmanageable
Solution Approach 1:
The patent performs preliminary analysis at the top hierarchy level to identify potential CDC structures and candidate blocks before full elaboration. By using high-level design information and clock domain information to pre-identify blocks that may contain CDC violations, the system avoids the time-consuming process of elaborating and analyzing the entire design, thus reducing processing time while maintaining accurate identification of CDC structures.
3Productivity
If modern computing systems attempt to manipulate electronic designs in their entirety, then complete analysis is possible, but system performance deteriorates to the point where many systems cannot handle the elaboration process
Solution Approach 1:
The patent extracts and isolates only those portions of the electronic design that contain potential CDC violations. By identifying candidate blocks at the top hierarchy level and selectively elaborating only those blocks rather than the entire design, the system reduces the complexity burden on computing systems while still achieving complete analysis of CDC-related structures.
Data Source
AI summary
Disclosed are techniques for verifying an electronic design using hierarchical clock domain crossing verification techniques. These techniques identify an electronic design including a top hierarchy and one or more instances at a first child hierarchy below the top hierarchy. The electronic design may be decomposed into a top hierarchy block for the top hierarchy and one or more child blocks for the one or more instances. A plurality of data structures may be generated by separately processing the top hierarchy block and the one or more child blocks on one or more computing nodes. One or more clock domain crossing structures may be identified in the electronic design at least by integrating the plurality of data structures.