Hierarchical Cell Verification via Electrical Property Classification
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Solution Overview
Problem
Traditional reliability verification tools for integrated circuit design struggle to efficiently handle the hierarchical data structure of large SoC designs, failing to combine physical and electrical verification effectively, which is crucial for ensuring robustness against premature or catastrophic electrical failures.
Innovation Solution
A method that analyzes circuit designs by identifying electrical properties of hierarchical cells, classifying instances based on these properties, and performing rule checking on selected groups to detect and address issues such as electrostatic discharge and electrical overstress, using geometric elements associated with components to modify the design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional verification tools are used to handle physical and electrical verification separately, then the verification process is simpler to implement, but the verification completeness and reliability are insufficient
Solution Approach 1:
The patent combines physical verification and electrical verification into a single integrated verification system. The system simultaneously performs both physical design rule checking and electrical rule checking (including ESD and EOS analysis) on circuit designs, eliminating the need for separate verification processes and achieving comprehensive reliability verification without proportionally increasing system complexity.
2Productivity
If hierarchical design methodology is employed to handle large SoC designs, then the design efficiency is improved, but the reliability verification efficiency does not improve as expected
Solution Approach 1:
The patent applies segmentation by classifying circuit blocks into different groups based on their electrical properties (such as voltage domains, power domains, and ESD protection requirements). This allows the verification system to process different types of circuit blocks using appropriate verification methods, improving verification efficiency while effectively managing the complexity of hierarchical SoC designs through property-based categorization.
Solution Approach 2:
The patent changes the verification approach by introducing electrical property parameters (voltage values, power domain characteristics, ESD protection levels) as the basis for classification and verification. This parameter-driven verification method enables the system to efficiently handle hierarchical designs by adapting verification strategies based on the electrical characteristics of different circuit blocks.
3Reliability
If comprehensive rule checking is performed on all circuit block instances, then the verification thoroughness is maximized, but the verification time and computational resources increase significantly
Solution Approach 1:
The patent implements partial verification by performing comprehensive electrical rule checking only on selected representative instances of circuit blocks rather than all instances. The system classifies circuit blocks into groups based on electrical properties and performs detailed verification on selected representatives from each group, achieving sufficient verification thoroughness while significantly reducing verification time and computational resources compared to checking every single instance.
Data Source
AI summary
A circuit design in a hierarchical description is analyzed. The analysis comprises identifying electrical properties of circuit blocks in the circuit design. Circuit components of the circuit design are associated with geometric elements of a layout design. Then instances of each of the circuit blocks are classified into groups of instances based on the electrical properties. Rule checking is performed on one or more groups in the groups of instances for each of the circuit blocks by analyzing geometric elements associate with components of one instance for each of the one or more groups.