Hierarchical Circuit Analysis Excluding Incomplete Components
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Solution Overview
Problem
Conventional EDA tools face challenges in analyzing electronic circuits with incomplete channel-connected components (CCCs) due to the requirement for complete circuits, leading to suboptimal design configurations and increased complexity, as existing methods either optimize for completeness at the cost of performance or require excessive analysis steps that may exceed tool capacity.
Innovation Solution
A method for hierarchical analysis that selects specific abstraction levels and focuses to identify incomplete circuits, generates design descriptions excluding these, and performs analysis on complete components, allowing for the generation of design rules to modify the General Design Model, thereby facilitating analysis of CCCs within larger sub-blocks or higher abstraction levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the design is repartitioned to ensure all devices making up a circuit are in the same sub-block, then circuit completeness is improved, but the sub-block is optimized for completeness rather than performance, resulting in non-optimal circuit design
Solution Approach 1:
The patent segments the analysis process into multiple hierarchical levels. At lower levels, incomplete CCCs are identified and excluded from analysis. At higher levels, these same CCCs are analyzed when complete. This segmentation allows each analysis level to work with appropriate data completeness without forcing sub-block boundaries to match circuit boundaries.
Solution Approach 2:
The patent introduces a temporal dimension to the analysis hierarchy by processing circuits at different abstraction levels in sequence. Incomplete CCCs are handled at lower levels, then the same circuits are analyzed again at higher levels when complete. This multi-dimensional approach resolves the contradiction between completeness and performance optimization.
2Reliability
If analysis is performed at a high enough level in the design hierarchy to avoid incomplete circuits, then complete circuits are analyzed, but substantial additional analysis steps are added that may exceed EDA tool capacity
Solution Approach 1:
The analysis is segmented into two distinct phases: (1) lower-level analysis that excludes incomplete CCCs to maintain manageable complexity, and (2) higher-level analysis that includes complete CCCs for comprehensive verification. This segmentation prevents tool capacity overload while ensuring complete circuit analysis.
Solution Approach 2:
At lower abstraction levels, the patent applies partial action by excluding only the incomplete CCC portions from analysis, rather than requiring complete circuit analysis at every level. This reduces analysis complexity at lower levels while maintaining the option for complete analysis at higher levels.
3Ease of operation
If estimation techniques are used for incomplete CCCs as in the Kumashiro approach, then analysis can proceed without complete circuits, but additional computation and estimation are required, increasing cost and complexity
Solution Approach 1:
The patent extracts incomplete CCCs from the analysis at lower levels and excludes them rather than applying estimation techniques. This removal eliminates the need for complex estimation computations while maintaining analysis feasibility through hierarchical processing.
Solution Approach 2:
The patent performs preliminary identification and exclusion of incomplete CCCs at lower abstraction levels before proceeding with analysis. This preliminary action prevents the need for complex estimation computations during the analysis phase, reducing overall computational complexity.
Data Source
AI summary
A method for hierarchical analysis of electronic circuits comprises selecting a first one of a plurality of abstraction levels of a general design model (GDM). The GDM comprises a first design description of electronic circuits at a plurality of abstraction levels and a plurality of foci, organized into sub-blocks. The method selects a first focus of the plurality of foci to select a first sub-block. The method identifies incomplete electronic circuits in the selected first sub-block. The method generates a second design description of the first sub-block to exclude identified incomplete electronic circuits, wherein the second design description is suitable for electronic design analysis (EDA). The method stores the generated second design description for subsequent use. Subsequent iterations thereby include all components of circuits that were incomplete in prior iterations.