Hierarchical Circuit Simulation Parallel Processing
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Solution Overview
Problem
Conventional circuit simulators, such as SPICE, face challenges in efficiently simulating large and complex integrated circuits due to high computational demands and memory requirements, exceeding the capabilities of current computer systems.
Innovation Solution
A method and system for hierarchical circuit simulation using parallel processing, where a circuit is divided into a top circuit and sub-circuit instances forming a hierarchy, allowing for iterative calculation of circuit equation parameters and signal values across multiple processors, enabling faster simulation while maintaining accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional circuit simulators (SPICE) are used to simulate large and complex integrated circuits, then simulation accuracy is maintained, but computational time and memory requirements become excessively high, exceeding current computer system capabilities
Solution Approach 1:
The circuit is divided into hierarchical levels with a top circuit and multiple sub-circuit instances (SCIs). Each SCI is further segmented into internal nets and external ports. This segmentation allows the simulation to process smaller sub-circuits independently and in parallel, significantly reducing computational time while maintaining overall simulation accuracy through systematic combination of results.
2Reliability
If conventional circuit simulators (SPICE) are used to simulate large and complex integrated circuits, then complete circuit analysis is performed, but memory requirements become excessively high, exceeding current computer system capabilities
Solution Approach 1:
The circuit analysis is segmented into hierarchical levels where each level processes a subset of the circuit. The top circuit level processes external ports and inter-SCI connections, while individual SCI levels process their internal nets. This segmentation divides the large memory requirement into smaller, manageable portions that can be handled by current computer systems.
Solution Approach 2:
The patent introduces a hierarchical dimension to the circuit simulation, organizing SCIs into levels under a top circuit. This hierarchical structure allows memory to be allocated and used at different levels of abstraction, reducing the peak memory requirements by processing circuits in a structured, multi-level approach rather than as a single monolithic system.
3Productivity
If the circuit is divided into hierarchical sub-circuit instances for parallel processing, then computational speed and memory efficiency are improved, but the complexity of managing the hierarchical structure and parallel computations increases
Solution Approach 1:
The patent develops a universal simulation framework that handles multiple functions: hierarchical decomposition, parallel processing coordination, circuit equation parameter calculation, and signal value determination. This multi-functional approach consolidates complexity into a unified system that manages all aspects of hierarchical simulation through standardized procedures and data structures.
Solution Approach 2:
The patent introduces intermediary components including a hierarchy manager that coordinates between the top circuit and sub-circuit instances, and standardized interfaces for passing circuit equation parameters and signal values between levels. These intermediaries simplify the management of hierarchical complexity by providing structured communication channels and coordination mechanisms.
Data Source
AI summary
A method for simulating a circuit represented by a top circuit and a plurality of subcircuit instances (SCIs) forming a hierarchy under the top circuit. The method comprises, during an iteration round of one or more iteration rounds, obtaining respective circuit equation parameters for each respective SCI of the plurality of SCIs in a bottom-up process, in which at least some of the circuit equation parameters for a parent SCI are obtained using a portion of the circuit equation parameters for a child SCI of the parent SCI. The method further comprises determining respective signal values of each respective SCI of the plurality of SCIs in a top-down process, where, for each child SCI having internal nets, signal values at internal nets of the child SCI are obtained using one or more signal values determined for a parent SCI and corresponding to one or more signal values at external ports of the child SCI.