Hierarchical Circuit Simulation Yield Assessment

The patent segments the large hierarchical circuit into multiple hierarchical levels (e.g., bitcell level, sense amplifier level, control logic level). Instead of simulating all 1,048,576 bitcells simultaneously, the simulation is divided into hierarchical segments where each level is simulated separately with aggregated results propagated upward. This segmentation reduces the computational burden from millions of simulations to a manageable number while maintaining yield assessment accuracy.

The patent uses extreme value probability distribution functions to create representative copies of transistor parameter variations. Rather than simulating every individual transistor instance with its specific random parameters, the method creates aggregated probability distributions that represent the statistical behavior of large numbers of transistors. These distributed copies capture the essential variability needed for yield assessment without requiring individual simulations of each component.

The patent transforms the simulation approach by changing from individual transistor parameter simulations to aggregated probability distribution functions. By parameterizing the transistor variations through statistical distributions (mean, standard deviation, and extreme values) rather than individual parameter instances, the method achieves reliable distribution tail visibility with far fewer simulations. This parameter transformation enables yield assessment without requiring millions of individual circuit simulations.

The patent performs preliminary statistical analysis to determine extreme value probability distribution functions before conducting the main simulations. By pre-characterizing the parameter variations and their distributions at each hierarchical level, the method prepares aggregated models that capture distribution tails in advance. This preliminary statistical characterization enables subsequent simulations to focus on circuit behavior rather than parameter sampling, improving productivity while maintaining precision.

The patent applies partial skewing rather than full pessimistic skewing to all devices. Instead of skewing every transistor to its extreme value (excessive action), the method selectively applies skewing based on the hierarchical level and the specific circuit's sensitivity to parameter variations. The aggregation process naturally accounts for the fact that not all devices will simultaneously exhibit extreme values, allowing designers to apply appropriate safety margins without over-constraining the design.

The patent enables different skewing strategies for different hierarchical levels and different circuit blocks based on their specific requirements. Rather than applying uniform pessimistic constraints across the entire design, the method allows local optimization where each hierarchical level (bitcell, sense amplifier, control logic) can be skewed according to its specific sensitivity and variability characteristics. This local quality approach maintains reliability where needed while reducing unnecessary complexity in less sensitive areas.