Hierarchical Circuit Timing Analysis and Modification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The place and route (P&R) process in electronic design automation is complex, error-prone, and time-consuming due to separate data management for top-level and block-level designs, leading to inflexible timing budget assignment and lengthy iterations for achieving timing closure.
Innovation Solution
The implementation of an in-hierarchy P&R process that maintains a hierarchical data structure, allowing direct timing analysis and modification by the top-level process to achieve both inter-block and intra-block timing closure without manual manipulation or additional data export/import, using a unified project file format and selective data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If separate data management is used for top-level and block-level designs, then design complexity is reduced at each level, but timing closure becomes lengthy and error-prone due to multiple iterations and manual manipulation
Solution Approach 1:
The patent merges top-level and block-level data into a unified hierarchical data structure that allows both levels to be managed simultaneously. The place and route tool accesses both top-level design data and block-level design data within a single processing environment, eliminating the need for separate data management cycles and manual file exchanges between different processing stages.
2Ease of manufacture
If separate engines process top-level and block-level designs, then each engine can be optimized for its specific task, but timing correlation problems and tool compatibility issues arise
Solution Approach 1:
The patent implements a universal place and route tool that can process both top-level and block-level designs within the same engine. This multi-functional approach allows the tool to handle different data granularities (individual cells at block-level, entire blocks at top-level) using a single processing framework, ensuring consistent timing correlation and eliminating tool compatibility issues while maintaining optimization capabilities.
3Stability of the object's composition
If designers only have access to data for their respective levels, then data security and modularity are maintained, but timing budget assignment becomes inflexible
Solution Approach 1:
The patent implements a nested hierarchical data structure where block-level design data is contained within the broader top-level design structure. This nesting allows designers to access and modify timing budgets at both levels simultaneously while maintaining the modular organization of design data. The hierarchical structure enables flexible timing budget assignment by allowing top-level designers to set inter-block timing constraints and block-level designers to optimize intra-block timing within those constraints.
4Manufacturing precision
If multiple iterations with extensive coordination are used, then timing closure can be achieved, but turn-around time becomes lengthy due to file export/import and data merging
Solution Approach 1:
The patent enables continuous timing analysis and optimization by maintaining both top-level and block-level design data in an accessible state throughout the place and route process. The tool can perform iterative timing closure operations without stopping to export/import files or switch between separate processing environments. This continuous action allows multiple timing analysis iterations to be performed rapidly, achieving timing closure with significantly reduced turn-around time while maintaining the coordination necessary for accurate timing closure.
Data Source
AI summary
Performing RC analysis in a hierarchical circuit design includes: accessing hierarchical circuit data in the hierarchical circuit design, the hierarchical circuit data comprising top-level data and lower-level block data; obtaining hierarchical RC information; combining RC information on boundary paths between blocks and RC information on boundary paths within blocks to generate boundary RC information; performing RC analysis using the boundary RC information to determine a timing delay; and comparing the timing delay with a desired delay to determine whether an RC timing is closed.