Hierarchical Circuit Timing Analysis with Merged Context
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Solution Overview
Problem
Conventional static timing analysis for multiple instances of a physical block in hierarchical circuit design often results in pessimistic or inefficient results due to lack of full knowledge of all instantiations, leading to sub-optimal design metrics such as power, performance, and area.
Innovation Solution
The approach involves determining a merged timing context information across all instances of a cell, calculating pseudo-slack for each instance, and applying timing credits to remove pessimism, thereby improving the accuracy and efficiency of timing analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If timing analysis is performed only once for the cell and used for each instance, then the analysis is efficient, but the timing analysis becomes highly pessimistic and conservative
Solution Approach 1:
The patent segments the timing analysis into two distinct phases: a first timing analysis performed once on the cell at a higher level of hierarchy, and second timing analyses performed separately for each instance at a lower level. This segmentation allows the system to achieve both efficiency (from the single first analysis) and accuracy (from the instance-specific second analyses), resolving the contradiction between productivity and measurement precision.
Solution Approach 2:
The patent applies preliminary action by performing the first timing analysis on the cell before the second timing analyses on individual instances. The first analysis establishes a baseline timing model that is then refined by subsequent instance-specific analyses, allowing the system to build accuracy progressively while maintaining overall efficiency.
2Measurement precision
If timing analysis is performed by enumeration of each instance to achieve better accuracy, then timing analysis accuracy improves, but the analysis becomes very slow and computation intensive
Solution Approach 1:
The patent divides the timing analysis process into hierarchical levels, performing a first analysis at a higher level that covers multiple instances simultaneously, and second analyses at a lower level for individual instances. This segmentation reduces the computational burden of analyzing each instance separately while maintaining accuracy, thus resolving the contradiction between precision and productivity.
Solution Approach 2:
The patent merges the timing analysis of multiple instances into a single first timing analysis performed at a higher level of hierarchy. By combining the analysis of multiple instances simultaneously rather than enumerating them separately, the system achieves both accuracy and efficiency, eliminating the need for separate analysis of each instance.
3Productivity
If the cell analysis does not have full knowledge of all instantiations, then the analysis remains simple and fast, but tighter timing constraints must be assumed leading to sub-optimal design metrics
Solution Approach 1:
The patent performs a preliminary first timing analysis on the cell at a higher level of hierarchy before performing instance-specific second analyses. This preliminary action establishes a baseline that incorporates knowledge of multiple instantiations, allowing the system to achieve both speed and reliable design optimization without assuming overly tight constraints.
Solution Approach 2:
The patent segments the timing analysis into hierarchical levels, allowing the first analysis to operate with limited knowledge for speed, while subsequent second analyses provide the necessary refinement based on full instantiation knowledge. This segmentation enables the system to maintain both productivity and reliability by performing analyses at appropriate levels with appropriate knowledge depths.
Data Source
AI summary
Embodiments perform static timing analysis using a digital representation of a circuit. The digital representation of the circuit includes multiple instances of a cell in a hierarchical cell block circuit. Timing context information is determined for each instance of the cell included in the circuit. A merged timing context information is determined to bound and cover each of the plurality of instances of the cell. A slack estimate is determined for a pair of ports for each instance of the cell. The instance with the smallest slack estimate is identified. A slack estimate for a pair of ports of the cell is determined based on the merged timing information of the cell. A timing credit is determined for the pair of ports based on the slack of the instance with the smallest slack and the slack estimate from the bound information for the pair of ports.