Hierarchical Circuit Verification via Tuple-Based Yield Estimation
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Solution Overview
Problem
Current variation-aware design tools are inadequate in handling statistical process variations, voltage, temperature, and environmental factors, particularly for large, hierarchically organized circuits with a low probability of failure and numerous voltage/temperature (VT) corners.
Innovation Solution
A computer-implemented method that generates sets of process and VT points, combines them into tuples, simulates sub-circuits, builds performance models, identifies failing tuples, and estimates yield by comparing performance metrics to target values, efficiently handling complex circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If comprehensive simulation of all process and VT corners is performed, then measurement precision and reliability are improved, but productivity and time consumption deteriorate
Solution Approach 1:
The patent performs preliminary simulation at selected tuples to build a performance model before conducting full verification. This preliminary action creates a predictive framework that identifies critical regions in the process-VT space, allowing subsequent verification to focus only on those regions rather than exhaustively simulating all corners, thus improving productivity while maintaining measurement precision.
Solution Approach 2:
The patent introduces a performance model as an intermediary between full-circuit simulation and failure identification. This model, built from selective simulation data, acts as a mediator that predicts performance at unsimulated tuples, enabling accurate failure identification without requiring exhaustive simulation of all process and VT corners.
2Reliability
If exhaustive simulation of all tuples is performed, then reliability is improved, but device complexity and computational resources worsen
Solution Approach 1:
The patent segments the verification process into distinct phases: (1) selective simulation at representative tuples to build a performance model, and (2) model-based evaluation of remaining tuples. This segmentation divides the complex exhaustive simulation task into manageable segments, reducing computational complexity while maintaining reliability through the model's ability to predict performance across the full space.
Solution Approach 2:
The patent performs partial simulation at selected tuples rather than exhaustive simulation of all tuples. By strategically selecting tuples that represent critical regions in the process-VT space and using the built model to infer performance at other tuples, the method achieves reliable yield estimation with reduced simulation complexity.
3Productivity
If hierarchical circuit structure is fully utilized, then productivity is improved, but measurement precision and detection difficulty worsen
Solution Approach 1:
The patent applies nested doll by performing verification at multiple hierarchical levels: sub-circuit level for building local performance models, and ECD level for global yield estimation. The sub-circuit models are nested within the broader ECD verification framework, allowing efficient local analysis to support accurate global assessment without requiring full ECD simulation for every tuple.
Solution Approach 2:
The patent uses sub-circuit performance models as intermediaries between hierarchical levels. These models mediate between detailed sub-circuit behavior and overall ECD performance, enabling accurate global failure rate measurement by aggregating results from selective sub-circuit simulations rather than requiring complete ECD simulation for all scenarios.
Data Source
AI summary
A computer-implemented method for quickly analyzing the effect of process, voltage, temperature, and other variations when the variation analysis or circuit structure can be hierarchically composed into nested loops. The method has two main steps: first, it hierarchically generates a set of points and inserts them into a flat list of tuples, where each tuple contains a point from each level in the looping hierarchy. Second, it efficiently identifies and simulates failing tuples with the assistance of modeling to order the tuples to simulate. By using the present method, a designer does not have to simulate the full ECD at each and every statistical process point or PVT corner, which can same considerable time or compute effort.