Hierarchical Clock Control with Hysteresis and Threshold Management

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Solution Overview

Problem

As integrated circuits become more dense and powerful, they face increasing power consumption challenges, particularly due to larger cache memories that consume more energy when idle, necessitating efficient power management strategies to conserve energy.

Innovation Solution

A powerdown mechanism that dynamically adjusts thresholds based on past usage history to selectively turn off clocks in lower hierarchy levels, using a master-slave unit configuration with hysteresis and threshold management to optimize performance and power trade-offs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If cache memory size is increased to reduce access latency, then performance is improved, but power consumption increases

Engineering Contradiction:
Improvememory access latencyVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The cache memory is divided into multiple hierarchy levels (L1, L2, L3 caches) with different sizes and access characteristics. Smaller, faster L1 cache is placed closer to execution units while larger, slower caches are positioned at lower levels, allowing the system to achieve fast access for frequently used data without requiring all data to reside in a single large memory structure, thus reducing overall power consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic clock control where the interface unit can turn off clocks to slave units during periods of non-use based on usage history and threshold conditions. This dynamic power management allows the cache hierarchy to adapt its power consumption in real-time, reducing energy waste during idle periods while maintaining performance when needed.

Inventive Principle:
Principle #15Dynamics

2Loss of energy

If cache memory is turned off during idle periods to save power, then energy efficiency is improved, but data loss occurs

Engineering Contradiction:
Improvepower wasteVSAvoiddata preservation
Core Design Contradiction:
Loss of energyVSLoss of information

Solution Approach 1:

Before turning off the slave unit clock, the interface unit checks usage history and determines if data needs to be preserved. When data must be maintained, the interface unit proactively copies data from the slave unit to the master unit before clock shutdown, ensuring data safety while still achieving power savings during idle periods.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The interface unit maintains usage history of the slave unit and uses this feedback information to determine when to turn off clocks and when to maintain power. The history tracking and threshold-based decision making create a closed-loop control system that adapts power management decisions based on actual usage patterns, preventing unnecessary data loss while maximizing energy efficiency.

Inventive Principle:
Principle #23Feedback

3Loss of energy

If clock threshold is set low to turn off slave unit quickly, then power efficiency is improved, but performance penalty increases

Engineering Contradiction:
Improvepower efficiencyVSAvoidperformance
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The patent implements dynamic threshold adjustment based on usage history. The interface unit modifies clock turn-off thresholds according to the slave unit's usage patterns, allowing the system to adapt between power-saving mode (higher thresholds) and performance-mode (lower thresholds) automatically, optimizing the balance between power efficiency and performance without manual intervention.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters (clock thresholds, turn-off timing) based on usage history and system state. By dynamically adjusting these parameters rather than using fixed values, the system can optimize power efficiency when appropriate while maintaining performance when needed, resolving the contradiction between power savings and performance maintenance.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9494997B2Hierarchical clock control using hysterisis and threshold management
Publication Date: 2016.11.15 APPLE INC
  • US9494997B2 patent drawing
  • US9494997B2 patent drawing
  • US9494997B2 patent drawing

AI summary

In some embodiments, a system may include a sub-hierarchy clock control. In some embodiments, the system may include a master unit. The master unit may include an interface unit electrically coupled to a slave unit. The interface unit may monitor, during use, usage requests of the slave unit by the master unit. In some embodiments, the interface unit may turn off clocks to the slave unit during periods of nonuse. In some embodiments, the interface unit may determine if a predetermined period of time elapses before turning on clocks to the slave unit such that turning off the slave unit resulted in the system achieving greater efficiency. In some embodiments, the interface unit may maintain, during use, power to the slave unit during periods of nonuse. The interface unit may maintain power to the slave unit during periods of nonuse such that data stored in the slave unit is preserved.