Hierarchical Clock Recovery for Multi-Phase PAM C-PHY Links
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Solution Overview
Problem
The C-PHY interface, commonly used in mobile devices, faces limitations in data throughput due to constraints in clock and data recovery circuits, particularly when using pulse amplitude modulation (PAM) beyond PAM-2, as the increased transition periods reduce available time for sampling and capturing symbols, leading to reduced data throughput.
Innovation Solution
The implementation of a data communication apparatus with multi-level comparison circuits and hierarchical clock recovery circuits that delay outputs to prevent adverse effects from multiple transitions at a single boundary, enabling improved clock recovery and data encoding using combinations of 3-phase encoding and PAM, such as PAM-4, to increase the number of signaling states and bits encoded per symbol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pulse amplitude modulation (PAM) beyond PAM-2 is used to increase data throughput, then the number of signaling states and bits encoded per symbol increases, but the transition periods increase which reduces available time for sampling and capturing symbols
Solution Approach 1:
The clock recovery circuit is divided into multiple hierarchical levels (first-level clock recovery circuits and second-level clock recovery circuit), each responsible for different aspects of clock signal generation. This segmentation allows parallel processing of multiple wires' transitions simultaneously, reducing the overall time required for clock recovery and symbol sampling.
Solution Approach 2:
The circuit performs preliminary detection of transitions on multiple wires before the actual sampling point. By detecting transitions in advance and using delay circuits to synchronize them, the system prepares the clock signal beforehand, ensuring that sampling occurs at the optimal moment without waiting for all transitions to complete.
2Reliability
If mask delay is increased to prevent adverse effects from multiple transitions at a single boundary, then clock recovery stability improves, but data throughput decreases due to loss of available symbols
Solution Approach 1:
The mask delay function is segmented across multiple hierarchical clock recovery levels. Instead of applying a single long mask delay, the first-level circuits apply shorter delays to individual wire transitions, and the second-level circuit combines these results. This distributes the delay burden, maintaining stability while minimizing overall symbol loss.
Solution Approach 2:
Rather than applying full mask delay to all transitions uniformly, the circuit applies partial masking selectively. The hierarchical structure allows the system to process transitions that occur outside the mask period at higher levels, effectively reducing the impact of mask delay on throughput while still preventing adverse effects from simultaneous transitions.
3Ease of manufacture
If conventional clock and data recovery circuits are used with multi-phase, multi-level encoding, then implementation is straightforward, but the maximum speed is limited by time variation related to transitions on different wires
Solution Approach 1:
The clock recovery function is segmented into hierarchical levels, with each level handling specific wires or transition detection tasks. This modular approach maintains ease of implementation while enabling the circuit to process multiple transitions in parallel, thereby increasing the maximum operating speed without overwhelming complexity.
Solution Approach 2:
The circuit transitions from processing transitions sequentially on individual wires to processing multiple wires' transitions simultaneously in a hierarchical structure. This dimensional change from single-wire to multi-wire parallel processing enables higher speeds while maintaining manageable complexity through structured organization.
Data Source
AI summary
An apparatus has a plurality of multi-level comparison circuits, each coupled to a pair of wires in a three-wire communication link, a plurality of first-level clock recovery circuits and a second-level clock recovery circuit. Each multi-level comparison circuit provides a multibit signal as an output. Each first-level clock recovery circuit includes a plurality of first-level flipflops clocked by transitions in a multibit signal received from one multi-level comparison circuit of the plurality of multi-level comparison circuits, and a first delay circuit that delays an output of the each first-level clock recovery circuit to provide a first reset signal that resets the each first-level clock recovery circuit. The second-level clock recovery circuit includes a second-level flipflop clocked by transitions in the outputs of the plurality of first-level clock recovery circuits, and a second delay circuit that delays an output of the second-level clock recovery circuit to provide a second reset signal to the second-level flipflop.