Hierarchical Clock Tree Construction for Integrated Circuits
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Solution Overview
Problem
Constructing hierarchical clock trees for integrated circuits is challenging, especially in abutted designs, due to the complexity of clock mesh design and high power consumption, which requires manual and time-consuming processes like clock tree synthesis and manual placement and routing of buffers.
Innovation Solution
An automated method for constructing a global clock tree based on top-level constraints, which includes constructing the global clock tree on a top level, pushing it down to block levels, generating block-level constraints, and modifying terminal configurations, allowing for efficient placement and routing, and handling multiple instantiated partitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If manual clock tree synthesis and manual placement and routing of buffers are used, then design flexibility and control are improved, but design time and complexity increase significantly
Solution Approach 1:
The patent divides the clock tree design into hierarchical levels (global clock tree at top level, local clock trees at block levels). This segmentation allows automated construction of the global clock tree while maintaining manual control over block-level designs, reducing overall design time while preserving necessary control flexibility.
Solution Approach 2:
The patent performs preliminary automated construction of the global clock tree at the top level before detailed block-level design. This preliminary action establishes the overall clock distribution framework, reducing the time required for subsequent detailed design work while maintaining design control at appropriate levels.
2Loss of time
If automated methods are used for clock tree construction, then design time is reduced, but design control and flexibility are lost
Solution Approach 1:
The patent segments the clock tree construction into automated top-level global clock tree synthesis and manual/block-level local clock tree design. This allows automated methods to reduce design time for the overall structure while preserving design control at the block level where detailed optimization is needed.
Solution Approach 2:
The patent applies different design approaches to different parts of the system: automated methods for the global clock tree where standardization benefits design efficiency, and manual/control-intensive methods for local clock trees where specific block requirements demand customized solutions.
3Area of stationary object
If clock mesh design is used for hierarchical designs, then area efficiency is improved, but power consumption and design complexity increase
Solution Approach 1:
The patent segments the clock distribution into hierarchical levels with a global clock tree for inter-block distribution and local clock trees for intra-block distribution. This segmentation achieves area efficiency by eliminating the need for a full mesh while maintaining controlled skew and latency through the hierarchical structure.
Solution Approach 2:
The patent extracts the clock distribution function into separate hierarchical levels, removing the need for a complex full-mesh clock mesh. The global clock tree extracts and distributes clock signals to block boundaries, while local clock trees handle internal block distribution, reducing overall power consumption and complexity.
4Area of stationary object
If abutted design without channels is used, then area is reduced, but clock signal distribution complexity increases
Solution Approach 1:
The patent segments the clock distribution network into global and local portions that interface at block boundaries. In abutted designs, the global clock tree endpoints are positioned at these boundaries, allowing clock signals to be distributed to adjacent blocks without requiring physical channels, thus maintaining area efficiency while managing complexity through hierarchical organization.
Solution Approach 2:
The patent resolves the complexity of abutted design clock distribution by moving the clock distribution interface to the temporal/hierarchical dimension rather than requiring physical spatial channels. The global clock tree distributes signals to block boundaries in the hierarchical domain, allowing adjacent blocks to share clock infrastructure without physical separation channels.
Data Source
AI summary
A method of automatically constructing a hierarchical clock tree for an integrated circuit may include constructing a global clock tree on a first level based on first-level constraints, pushing the global clock tree to partitions on a second level, and generating second-level constraints for the partitions on the second level. The second-level constraints may be included in configuration files that may be generated for the partitions on the second level. The first-level constraints may be included in a first-level configuration file that is user-modifiable. The second-level constraints may include information for replicating multiple instantiated partitions on the second level. The method may further include modifying terminal names and/or configurations after pushdown. The method may further include creating infrastructure to analyze timing of the global clock tree.