Hierarchical Color Decomposition for IC Mask Patterning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated circuit design faces challenges in accurate layout verification and manufacturing due to the limitations of single mask patterning, particularly with deep sub-micron features, leading to odd-cycle violations and increased complexity in Double Patterning Lithography (DPL), which results in inefficiencies and re-work during chip assembly.
Innovation Solution
A hierarchical color decomposition of library cells with boundary-aware color selection is implemented, allowing for the creation of hierarchical hand-off regions by pinning edge cells to specific masks and prohibiting even-numbered cell configurations, enabling correct-by-construction color decompositions and reducing re-work by allowing different-color spacings between edge and internal cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If single mask patterning is used for deep sub-micron features, then manufacturing process is simple, but layout verification accuracy deteriorates due to odd-cycle violations
Solution Approach 1:
The patent segments the mask assignment problem into hierarchical levels, assigning colors to cells at different hierarchy levels independently. This segmentation allows the complex single-mask verification problem to be broken down into manageable sub-problems at each hierarchy level, enabling accurate verification while maintaining manufacturing simplicity.
Solution Approach 2:
The patent introduces a hierarchical dimension to the traditional planar cell coloring problem. By transitioning from 2D cell-level coloring to multi-level hierarchical coloring, the system can resolve odd-cycle violations that occur in single-mask patterning while maintaining the simplicity of the mask process itself.
2Manufacturing precision
If Double Patterning Lithography is implemented, then manufacturing precision improves, but device complexity increases due to increased process steps
Solution Approach 1:
The patent performs preliminary color decomposition and mask assignment at the hierarchy level before physical manufacturing. By pre-resolving coloring conflicts and validating mask assignments computationally, the system eliminates the need for complex iterative adjustments during actual DPL processing, thereby reducing operational complexity while maintaining precision.
Solution Approach 2:
The hierarchical coloring system automatically resolves mask assignment conflicts through bottom-up propagation and top-down validation. The system self-corrects odd-cycle violations without requiring external intervention or complex manual adjustment, reducing the operational burden despite the increased precision requirements of DPL.
3Productivity
If conventional cell placement is used, then placement speed is fast, but re-work increases due to odd-cycle violations requiring corrections
Solution Approach 1:
The patent implements feedback mechanisms at multiple levels: bottom-up color propagation that automatically adjusts cell assignments based on constraint violations, and top-down validation that checks for odd-cycle violations before final placement. This multi-level feedback system prevents re-work by catching and correcting issues during the placement process itself rather than after completion.
Solution Approach 2:
The system performs preliminary color decomposition and conflict resolution before final cell placement is locked in. By pre-identifying and resolving odd-cycle violations at the hierarchy level, the system ensures that placement decisions are made with conflict-free color assignments, eliminating the need for costly re-work corrections later in the design flow.
Data Source
AI summary
Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of a color decomposition of library cells having boundary-aware color selection. A non-limiting example computer-implemented method includes placing a plurality of shapes within a hierarchical level of a chip design. The plurality of shapes can include a top boundary shape, a bottom boundary shape, one or more center boundary shapes, and one or more internal shapes. A hierarchical hand-off region is constructed by pinning the top boundary shape to a first mask, pinning the bottom boundary shape to a second mask, and pinning the one or more center boundary shapes to a same mask. The same mask is selected from one of the first mask and the second mask.