Hierarchical Common Source Line for NAND Flash Power Reduction
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Solution Overview
Problem
In NAND flash memory, the reduction in main supply voltage (VDD) level has reduced the effectiveness of self-boosting methods to prevent program disturb, as they require higher bit line voltages to inhibit programming in unselected cells, leading to power consumption issues and inefficiencies in programming operations.
Innovation Solution
A hierarchical common source-line structure is implemented, utilizing a local switch logic unit with semiconductor switches to selectively control the global common source line, allowing only the selected NAND flash cell block to receive the signal and voltage, while isolating unselected blocks, thereby reducing power consumption and preventing program disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self-boosting method is used to prevent program disturb, then program disturb is reduced, but power consumption increases due to requirement of higher bit line voltages
Solution Approach 1:
The memory array is divided into multiple blocks, each with its own local common source line. During programming operations, only the selected block's source line is activated while others remain isolated. This segmentation allows voltage boosting to be applied locally only where needed, preventing program disturb in the selected block without requiring high voltages across all blocks, thus reducing overall power consumption.
Solution Approach 2:
The patent implements local voltage boosting by applying high voltages only to the bit lines and source line of the selected block, while unselected blocks operate at normal voltages. This local quality approach ensures that the energy-intensive self-boosting operation is confined to the minimal necessary region, maintaining program disturb prevention where needed while minimizing power consumption across the entire memory array.
2Productivity
If program voltage is applied to control gate of flash memory cell, then programming is achieved, but unselected cells on the same word line are inadvertently programmed
Solution Approach 1:
The memory is organized into multiple blocks with separate local common source lines. By isolating unselected blocks through their respective local switch logic units, the patent ensures that programming operations on one block do not affect other blocks. This segmentation allows aggressive programming voltages to be applied to the selected block without causing program disturb in unselected blocks, maintaining both programming speed and reliability.
Solution Approach 2:
The local common source line acts as an intermediary between the global word lines and the memory cells within each block. By controlling the voltage potential of each block's source line independently through local switch logic, the patent prevents unwanted charge injection into unselected blocks while allowing efficient programming in the selected block, thus resolving the program disturb issue without sacrificing programming speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and enhances programming efficiency by isolating unselected blocks, allowing for effective voltage control and minimizing accidental programming, thus improving the overall performance of NAND flash memory operations.
Implementation Method 1
A hierarchical common source-line structure is implemented, utilizing a local switch logic unit with semiconductor switches to selectively control the global common source line, allowing only the selected NAND flash cell block to receive the signal and voltage, while isolating unselected blocks
Data Source
AI summary
Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.