Hierarchical Compaction for IC Test Power Control
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Solution Overview
Problem
Current test pattern compaction methods for integrated circuits often lead to excessive power dissipation during testing, potentially damaging low-power devices and causing false failure indications, as they do not adequately manage power levels during the release or capture portions of the test, especially in low-power designs.
Innovation Solution
A hierarchical compaction method that categorizes test patterns based on specific criteria such as clock gate control, flip-flop count, and adjacency, allowing for fine-grained control of power constraints, merging test patterns only if they meet all criteria within each hierarchical level to form compacted test patterns that minimize power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If test patterns are compacted using traditional methods that only check for care bit conflicts, then the number of test patterns is reduced, but power dissipation during testing increases excessively
Solution Approach 1:
The patent segments the test pattern compaction process into multiple hierarchical levels: (1) basic care bit conflict checking, (2) clock gate control grouping, (3) flip-flop count constraints, and (4) adjacency constraints. Each level applies specific power management criteria, allowing the system to reduce test patterns while maintaining power dissipation within safe limits through progressive filtering at each segmentation level.
2Loss of time
If test patterns are merged without considering power constraints, then test time is reduced, but low-power devices may be damaged from excessive power
Solution Approach 1:
The patent applies preliminary action by evaluating power constraints before merging test patterns. The hierarchical compaction process checks clock gate control compatibility, flip-flop count limits, and adjacency constraints prior to pattern merging. This preliminary verification ensures that only power-safe pattern combinations are merged, preventing device damage while still achieving test time reduction through valid compaction.
3Productivity
If traditional compaction methods are used that only check care bit conflicts, then pattern merging is maximized, but false failure indications increase
Solution Approach 1:
The patent implements feedback mechanisms at each hierarchical level of compaction. After merging patterns based on care bit conflicts, the system evaluates whether the merged patterns satisfy clock gate control grouping, flip-flop count constraints, and adjacency requirements. Patterns that fail these feedback checks are separated rather than merged, preventing false failure indications while maintaining high pattern merging efficiency for valid combinations.
4Loss of energy
If power management constraints are strictly applied during pattern compaction, then power dissipation is controlled, but the number of test patterns increases
Solution Approach 1:
The patent applies merging at multiple hierarchical levels to maximize pattern consolidation while maintaining power control. At each level (clock gate grouping, flip-flop count, adjacency), compatible patterns are merged into compacted patterns. This multi-level merging approach achieves the maximum possible pattern reduction subject to power constraints, rather than applying a single conservative limit that would leave more patterns separate.
Data Source
AI summary
A method and apparatus for hierarchical compaction of test patterns to be applied to an integrated circuit during test is disclosed. The embodiments apply a hierarchical strategy for categorizing test patterns for compaction. A test pattern is considered against a series of criteria for a compacted test pattern. Where all the criteria are met the test pattern is merged into a compacted test pattern. If the criteria are not all met the test patterns are considered against each of the compacted test patterns in turn. This is repeated for each test pattern to create a set of compacted test patterns conforming to the requirements of the criteria. This method and apparatus provides for fine grained control of low power constraints when testing integrated circuits, and includes benefits such as preventing damage during test from burnout and hot spots, and avoiding failures due to IR drop.