Hierarchical Core Valid Tracking for Precise Cache Coherency

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Solution Overview

Problem

Conventional cache coherency tracking mechanisms in multi-core processors suffer from increased complexity and inefficiency due to coarse-grained tracking, leading to excessive cache/snoop traffic and performance degradation, particularly in systems with complex sharing patterns and large core counts.

Innovation Solution

Implementing hierarchical core valid (CV) tracking technology that utilizes a hierarchical data structure to precisely track core ownership, independent of physical topology, allowing for fine-grained tracking of core associations and reducing false aliasing through a bit vector format that includes cluster, sub-cluster, and relative logical ID fields.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If coarse-grained tracking is used in conventional cache coherency mechanisms, then device complexity is reduced, but cache/snoop traffic increases and performance degrades

Engineering Contradiction:
Improvetracking mechanism complexityVSAvoidcache coherency performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments the core tracking mechanism into hierarchical levels: directory-level tracking for coarse-grained groups and snoop filter-level tracking for fine-grained individual core identification. This segmentation allows the system to maintain low complexity at the directory level while achieving high performance through precise tracking at the snoop filter level, resolving the contradiction between simplicity and effectiveness.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If coarse-grained tracking is used, then device complexity is reduced, but fabric bandwidth loss increases

Engineering Contradiction:
Improvetracking mechanism complexityVSAvoidfabric bandwidth loss
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The hierarchical tracking structure segments bandwidth consumption by allowing directory operations to use compact group identifiers while snoop operations use precise core-level identification. This reduces unnecessary fabric traffic by avoiding broad broadcasts, thereby reducing fabric bandwidth loss without significantly increasing device complexity.

Inventive Principle:
Principle #1Segmentation

3Measurement precision

If fine-grained tracking is implemented, then cache coherency precision is improved, but device complexity increases

Engineering Contradiction:
Improvecore ownership tracking precisionVSAvoidtracking mechanism complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces a hierarchical dimension to the tracking mechanism, organizing core identification into multiple levels (directory level and snoop filter level). This dimensional organization allows precise fine-grained tracking at the snoop filter level while maintaining simpler structures at higher levels, thereby achieving high precision without proportionally increasing overall device complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Productivity

If fine-grained tracking is implemented, then performance is improved, but false aliasing occurs with coarse-grained methods

Engineering Contradiction:
Improveapplication/workload performanceVSAvoidtracking accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the tracking function between directory and snoop filter, with the snoop filter performing fine-grained tracking to eliminate false aliasing. This segmentation ensures high reliability in core ownership identification, which directly improves application and workload performance by preventing incorrect coherency decisions.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12554644B2Hierarchical core valid tracker for cache coherency
Publication Date: 2026.02.17 INTEL CORP
  • US12554644B2 patent drawing
  • US12554644B2 patent drawing
  • US12554644B2 patent drawing

AI summary

Techniques and mechanisms to provide hierarchical core valid tracking. In an embodiment, an apparatus comprises a cache to store information accessible by two or more cores, and circuitry coupled to the cache to maintain coherence of the information stored in the cache. The circuitry is further to hierarchically track respective associations of the information stored in the cache with the two or more cores. In another embodiment, a lowest hierarchical level of the hierarchically tracked associations is to indicate a logical core identifier of a particular core of the two or more cores.