Hierarchical Counter Architecture for High-Speed Network Statistics
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Solution Overview
Problem
High-speed network switches face challenges in efficiently storing and updating statistics counters due to the tradeoff between using expensive on-chip SRAM and the limitations of off-chip DRAM, where there is a need to balance the number of counters to avoid integer overflow while efficiently utilizing memory resources.
Innovation Solution
The implementation of hierarchical statistically multiplexed counters, which dynamically concatenate P base counters with S subcounters across multiple levels, using an overflow FIFO to extend counter life, allowing for flexible expansion and shrinkage of counter capacity and handling overflows by shifting values between levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If off-chip DRAM is used to store counters, then memory cost is reduced, but counter update speed is insufficient for high-speed networks
Solution Approach 1:
The counter storage is segmented into multiple hierarchical levels (Level 0, Level 1, Level 2, etc.), where Level 0 contains the most frequently accessed counters in fast on-chip memory, and higher levels contain less frequently accessed counters in slower off-chip memory. This segmentation allows the system to optimize for both speed and cost by placing only necessary counters in expensive fast memory.
Solution Approach 2:
The patent introduces a hierarchical dimension to counter storage, organizing counters in a tree-like structure with multiple levels rather than a single flat storage layer. This dimensional change enables the system to balance speed and cost by distributing counters across different memory technologies at different hierarchical levels.
2Measurement precision
If the number of counters is increased to avoid integer overflow, then counter accuracy is improved, but memory resource utilization becomes inefficient
Solution Approach 1:
The counter width is made dynamic rather than static. Each counter can adjust its width based on the actual traffic patterns and counting requirements. Counters that experience high traffic are allocated more bits to prevent overflow, while counters with low traffic use fewer bits, optimizing memory utilization while maintaining accuracy where needed.
Solution Approach 2:
The patent changes the parameter of counter width from a fixed value to a variable that can be adjusted based on traffic conditions. This parameter change allows the system to optimize between accuracy and memory usage by allocating counter width dynamically according to actual needs rather than provisioning for worst-case scenarios across all counters.
Data Source
AI summary
Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.