Hierarchical CPU Control for Parallel Machine Learning Tasks
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Solution Overview
Problem
Data processing systems with central processing units (CPUs) face inefficiencies in handling computationally-intensive tasks like machine learning due to the need for centralized control of hardware accelerators, which leads to performance overheads and resource contention.
Innovation Solution
A data processing system with a hierarchical CPU architecture comprising a first-level CPU, a second-level CPU, and a plurality of third-level CPUs, where each third-level CPU is associated with a hardware accelerator, allowing decentralized control and asynchronous task delegation, reducing overheads and improving performance through parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a centralized CPU controls hardware accelerators for machine learning tasks, then the system can maintain simple architecture and centralized control, but performance overhead increases and resource contention occurs
Solution Approach 1:
The system divides the centralized control architecture into a hierarchical structure with first-level CPUs for system-wide coordination and second-level CPUs for accelerator-specific control. This segmentation distributes the control burden, reducing overhead on individual processors while improving overall machine learning processing efficiency through specialized handling at each level.
2Ease of operation
If a single CPU coordinates all hardware accelerators, then control flow is simplified, but resource contention increases and latency rises
Solution Approach 1:
Second-level CPUs act as intermediaries between first-level CPUs and hardware accelerators. This intermediary layer maintains simplified control flow at the system level while reducing latency and resource contention at the accelerator interface, as second-level CPUs are dedicated to coordinating multiple accelerators without competing for system-wide resources.
3Use of energy by moving object
If hardware accelerators are shared across multiple CPUs, then resource utilization improves, but resource contention increases
Solution Approach 1:
The system introduces a hierarchical dimension to accelerator access, with second-level CPUs dedicated to specific accelerator groups. This dimensional organization allows multiple first-level CPUs to share accelerators through dedicated intermediaries, maintaining high resource utilization while eliminating direct contention between first-level CPUs by routing all accelerator access through the second level.
4Productivity
If a hierarchical CPU structure is implemented, then parallel processing capability increases, but device complexity increases
Solution Approach 1:
Each level of the CPU hierarchy is designed with universal functionality to handle multiple types of machine learning accelerators and workloads. First-level CPUs can coordinate any accelerator through second-level intermediaries, and second-level CPUs can manage multiple different accelerator types. This universality enables parallel processing across diverse hardware while keeping the hierarchical structure manageable through standardized interfaces and protocols.
Data Source
AI summary
A data processing method comprises: executing at least one operation on a first-level CPU, the at least one operation configured to cause a machine learning process to initiate; and issuing a request to a second-level CPU configured to coordinate a plurality of third-level CPUs to perform at least part of the machine learning process, wherein the first-level CPU and the second-level CPU run separate operating systems.